| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mailbox/ |
| D | ti,omap-mailbox.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
26 interrupt configuration registers, and have a rx and tx interrupt source per
28 appropriate programming of the rx and tx interrupt sources on the appropriate
35 lines can also be routed to different processor sub-systems on DRA7xx as they
49 within a SoC. The sub-mailboxes (actual communication channels) are
56 "mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt
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| D | hisilicon,hi6220-mailbox.txt | 13 --------------------
14 - compatible: Shall be "hisilicon,hi6220-mbox"
15 - reg: Contains the mailbox register address range (base
19 - #mbox-cells: Common mailbox binding property to identify the number
23 slot_id: Slot id used either for TX or RX
26 TX/RX interrupt to application processor,
28 - interrupts: Contains the interrupt information for the mailbox
33 --------------------
34 - hi6220,mbox-tx-noirq: Property of MCU firmware's feature, so mailbox driver
40 --------
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/ti/ |
| D | k3-j721e-som-p0.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include "k3-j721e.dtsi"
18 reserved_memory: reserved-memory {
19 #address-cells = <2>;
20 #size-cells = <2>;
26 no-map;
29 c66_1_dma_memory_region: c66-dma-memory@a6000000 {
30 compatible = "shared-dma-pool";
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mailbox/ |
| D | omap-mailbox.txt | 16 programmable through a set of interrupt configuration registers, and have a rx
18 is achieved through the appropriate programming of the rx and tx interrupt
25 routed to different processor sub-systems on DRA7xx as they are routed through
35 a SoC. The sub-mailboxes are represented as child nodes of this parent node.
38 --------------------
39 - compatible: Should be one of the following,
40 "ti,omap2-mailbox" for OMAP2420, OMAP2430 SoCs
41 "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs
42 "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx,
44 "ti,am654-mailbox" for K3 AM65x and J721E SoCs
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| D | hisilicon,hi6220-mailbox.txt | 13 --------------------
14 - compatible: Shall be "hisilicon,hi6220-mbox"
15 - reg: Contains the mailbox register address range (base
19 - #mbox-cells: Common mailbox binding property to identify the number
23 slot_id: Slot id used either for TX or RX
26 TX/RX interrupt to application processor,
28 - interrupts: Contains the interrupt information for the mailbox
33 --------------------
34 - hi6220,mbox-tx-noirq: Property of MCU firmware's feature, so mailbox driver
40 --------
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| D | sti-mailbox.txt | 7 ----------
10 - compatible : Should be "st,stih407-mailbox"
11 - reg : Offset and length of the device's register set
12 - mbox-name : Name of the mailbox
13 - #mbox-cells: : Must be 2
20 - interrupts : Contains the IRQ line for a Rx mailbox
25 compatible = "st,stih407-mailbox";
28 #mbox-cells = <2>;
29 mbox-name = "a9";
33 ------
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| /kernel/linux/linux-6.6/drivers/media/platform/amphion/ |
| D | vpu_mbox.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2020-2021 NXP
19 struct vpu_mbox *rx = container_of(cl, struct vpu_mbox, cl); in vpu_mbox_rx_callback() local
20 struct vpu_core *core = container_of(rx, struct vpu_core, rx); in vpu_mbox_rx_callback()
25 static int vpu_mbox_request_channel(struct device *dev, struct vpu_mbox *mbox) in vpu_mbox_request_channel() argument
30 if (!dev || !mbox) in vpu_mbox_request_channel()
31 return -EINVAL; in vpu_mbox_request_channel()
32 if (mbox->ch) in vpu_mbox_request_channel()
35 cl = &mbox->cl; in vpu_mbox_request_channel()
36 cl->dev = dev; in vpu_mbox_request_channel()
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| /kernel/linux/linux-5.10/drivers/firmware/tegra/ |
| D | bpmp-tegra186.c | 1 // SPDX-License-Identifier: GPL-2.0
11 #include <soc/tegra/bpmp-abi.h>
14 #include "bpmp-private.h"
23 } tx, rx; member
28 } mbox; member
36 priv = container_of(client, struct tegra186_bpmp, mbox.client); in mbox_client_to_bpmp()
38 return priv->parent; in mbox_client_to_bpmp()
45 frame = tegra_ivc_read_get_next_frame(channel->ivc); in tegra186_bpmp_is_message_ready()
47 channel->ib = NULL; in tegra186_bpmp_is_message_ready()
51 channel->ib = frame; in tegra186_bpmp_is_message_ready()
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| /kernel/linux/linux-6.6/drivers/firmware/tegra/ |
| D | bpmp-tegra186.c | 1 // SPDX-License-Identifier: GPL-2.0
13 #include <soc/tegra/bpmp-abi.h>
16 #include "bpmp-private.h"
28 } tx, rx; member
33 } mbox; member
41 priv = container_of(client, struct tegra186_bpmp, mbox.client); in mbox_client_to_bpmp()
43 return priv->parent; in mbox_client_to_bpmp()
50 err = tegra_ivc_read_get_next_frame(channel->ivc, &channel->ib); in tegra186_bpmp_is_message_ready()
52 iosys_map_clear(&channel->ib); in tegra186_bpmp_is_message_ready()
63 err = tegra_ivc_write_get_next_frame(channel->ivc, &channel->ob); in tegra186_bpmp_is_channel_free()
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/ti/ |
| D | k3-j721e-som-p0.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include "k3-j721e.dtsi"
20 reserved_memory: reserved-memory {
21 #address-cells = <2>;
22 #size-cells = <2>;
28 no-map;
31 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
32 compatible = "shared-dma-pool";
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| D | k3-am642-tqma64xxl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany.
7 #include "k3-am642.dtsi"
18 /* 1G RAM - default variant */
23 reserved-memory {
24 #address-cells = <2>;
25 #size-cells = <2>;
31 no-map;
34 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
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| D | k3-j784s4-evm.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include <dt-bindings/net/ti-dp83867.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include "k3-j784s4.dtsi"
15 compatible = "ti,j784s4-evm", "ti,j784s4";
19 stdout-path = "serial2:115200n8";
39 reserved_memory: reserved-memory {
40 #address-cells = <2>;
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| /kernel/linux/linux-5.10/drivers/mailbox/ |
| D | zynqmp-ipi-mailbox.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/arm-smccc.h>
15 #include <linux/mailbox/zynqmp-ipi-message.h>
55 #define IPI_MB_CHNL_RX 1 /* IPI mailbox RX channel */
58 * struct zynqmp_ipi_mchan - Description of a Xilinx ZynqMP IPI mailbox channel
78 * struct zynqmp_ipi_mbox - Description of a ZynqMP IPI mailbox
84 * @mbox: mailbox Controller
85 * @mchans: array for channels, tx channel and rx channel.
92 struct mbox_controller mbox; member
97 * struct zynqmp_ipi_pdata - Description of z ZynqMP IPI agent platform data.
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| D | imx-mailbox.c | 1 // SPDX-License-Identifier: GPL-2.0
19 #define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x)))
20 #define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x)))
21 #define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x)))
25 #define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x)))
27 #define IMX_MU_xCR_RIEn(x) BIT(24 + (3 - (x)))
29 #define IMX_MU_xCR_TIEn(x) BIT(20 + (3 - (x)))
31 #define IMX_MU_xCR_GIRn(x) BIT(16 + (3 - (x)))
34 /* TX0/RX0/RXDB[0-3] */
40 IMX_MU_TYPE_RX, /* Rx */
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| /kernel/linux/linux-6.6/drivers/mailbox/ |
| D | zynqmp-ipi-mailbox.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/arm-smccc.h>
15 #include <linux/mailbox/zynqmp-ipi-message.h>
53 #define IPI_MB_CHNL_RX 1 /* IPI mailbox RX channel */
56 * struct zynqmp_ipi_mchan - Description of a Xilinx ZynqMP IPI mailbox channel
76 * struct zynqmp_ipi_mbox - Description of a ZynqMP IPI mailbox
82 * @mbox: mailbox Controller
83 * @mchans: array for channels, tx channel and rx channel.
90 struct mbox_controller mbox; member
95 * struct zynqmp_ipi_pdata - Description of z ZynqMP IPI agent platform data.
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| D | imx-mailbox.c | 1 // SPDX-License-Identifier: GPL-2.0
24 /* TX0/RX0/RXDB[0-3] */
35 /* Please not change TX & RX */
38 IMX_MU_TYPE_RX = 1, /* Rx */
40 IMX_MU_TYPE_RXDB = 3, /* Rx doorbell */
85 struct mbox_controller mbox; member
108 int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp); member
118 #define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
119 #define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
120 #define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/ti/omap/ |
| D | omap2420.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
15 compatible = "ti,omap2-l4", "simple-bus";
16 #address-cells = <1>;
17 #size-cells = <1>;
21 compatible = "ti,omap2-prcm";
25 #address-cells = <1>;
26 #size-cells = <0>;
34 compatible = "ti,omap2-scm", "simple-bus";
36 #address-cells = <1>;
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| D | dra72x.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
20 compatible = "arm,cortex-a15-pmu";
21 interrupt-parent = <&wakeupgen>;
27 target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
28 compatible = "ti,sysc-omap4", "ti,sysc";
31 reg-names = "rev", "sysc";
32 ti,sysc-midle = <SYSC_IDLE_FORCE>,
34 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
37 clock-names = "fck";
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| D | dra74x.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
16 compatible = "arm,cortex-a15";
18 operating-points-v2 = <&cpu0_opp_table>;
21 clock-names = "cpu";
23 clock-latency = <300000>; /* From omap-cpufreq driver */
26 #cooling-cells = <2>; /* min followed by max */
28 vbb-supply = <&abb_mpu>;
40 compatible = "arm,cortex-a15-pmu";
41 interrupt-parent = <&wakeupgen>;
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | dra72x.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
20 compatible = "arm,cortex-a15-pmu";
21 interrupt-parent = <&wakeupgen>;
27 target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
28 compatible = "ti,sysc-omap4", "ti,sysc";
31 reg-names = "rev", "sysc";
32 ti,sysc-midle = <SYSC_IDLE_FORCE>,
34 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
37 clock-names = "fck";
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| D | dra74x.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
16 compatible = "arm,cortex-a15";
18 operating-points-v2 = <&cpu0_opp_table>;
21 clock-names = "cpu";
23 clock-latency = <300000>; /* From omap-cpufreq driver */
26 #cooling-cells = <2>; /* min followed by max */
28 vbb-supply = <&abb_mpu>;
40 compatible = "arm,cortex-a15-pmu";
41 interrupt-parent = <&wakeupgen>;
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| D | omap2420.dtsi | 4 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
18 compatible = "ti,omap2-l4", "simple-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
24 compatible = "ti,omap2-prcm";
28 #address-cells = <1>;
29 #size-cells = <0>;
37 compatible = "ti,omap2-scm", "simple-bus";
39 #address-cells = <1>;
40 #size-cells = <1>;
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/ |
| D | amphion,vpu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ming Qian <ming.qian@nxp.com>
12 - Shijie Qin <shijie.qin@nxp.com>
14 description: |-
20 pattern: "^vpu@[0-9a-f]+$"
24 - enum:
25 - nxp,imx8qm-vpu
26 - nxp,imx8qxp-vpu
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| /kernel/linux/linux-5.10/drivers/net/ethernet/marvell/octeontx2/af/ |
| D | mbox.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
37 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
39 #define MBOX_RSP_TIMEOUT 2000 /* Time(ms) to wait for mbox response */
41 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */
54 void *mbase; /* This dev's mbox region */
64 void *hwbase; /* Mbox region advertised by HW */
66 u64 trigger; /* Trigger mbox notification */
67 u16 tr_shift; /* Mbox trigger shift */
68 u64 rx_start; /* Offset of Rx region in mbox memory */
69 u64 tx_start; /* Offset of Tx region in mbox memory */
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/ |
| D | imx8-ss-vpu.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
8 #address-cells = <1>;
9 #size-cells = <1>;
12 power-domains = <&pd IMX_SC_R_VPU>;
16 compatible = "fsl,imx6sx-mu";
19 #mbox-cells = <2>;
20 power-domains = <&pd IMX_SC_R_VPU_MU_0>;
25 compatible = "fsl,imx6sx-mu";
28 #mbox-cells = <2>;
29 power-domains = <&pd IMX_SC_R_VPU_MU_1>;
[all …]
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