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/kernel/linux/linux-6.6/drivers/net/ethernet/cavium/liquidio/
Docteon_mailbox.c31 * @mbox: Pointer mailbox
33 * Reads the 8-bytes of data from the mbox register
36 int octeon_mbox_read(struct octeon_mbox *mbox) in octeon_mbox_read() argument
41 spin_lock(&mbox->lock); in octeon_mbox_read()
43 msg.u64 = readq(mbox->mbox_read_reg); in octeon_mbox_read()
46 spin_unlock(&mbox->lock); in octeon_mbox_read()
50 if (mbox->state & OCTEON_MBOX_STATE_REQUEST_RECEIVING) { in octeon_mbox_read()
51 mbox->mbox_req.data[mbox->mbox_req.recv_len - 1] = msg.u64; in octeon_mbox_read()
52 mbox->mbox_req.recv_len++; in octeon_mbox_read()
54 if (mbox->state & OCTEON_MBOX_STATE_RESPONSE_RECEIVING) { in octeon_mbox_read()
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/cavium/liquidio/
Docteon_mailbox.c31 * @mbox: Pointer mailbox
33 * Reads the 8-bytes of data from the mbox register
36 int octeon_mbox_read(struct octeon_mbox *mbox) in octeon_mbox_read() argument
41 spin_lock(&mbox->lock); in octeon_mbox_read()
43 msg.u64 = readq(mbox->mbox_read_reg); in octeon_mbox_read()
46 spin_unlock(&mbox->lock); in octeon_mbox_read()
50 if (mbox->state & OCTEON_MBOX_STATE_REQUEST_RECEIVING) { in octeon_mbox_read()
51 mbox->mbox_req.data[mbox->mbox_req.recv_len - 1] = msg.u64; in octeon_mbox_read()
52 mbox->mbox_req.recv_len++; in octeon_mbox_read()
54 if (mbox->state & OCTEON_MBOX_STATE_RESPONSE_RECEIVING) { in octeon_mbox_read()
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/marvell/octeontx2/af/
Dmbox.c13 #include "mbox.h"
18 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid) in __otx2_mbox_reset() argument
20 struct otx2_mbox_dev *mdev = &mbox->dev[devid]; in __otx2_mbox_reset()
24 tx_hdr = hw_mbase + mbox->tx_start; in __otx2_mbox_reset()
25 rx_hdr = hw_mbase + mbox->rx_start; in __otx2_mbox_reset()
36 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid) in otx2_mbox_reset() argument
38 struct otx2_mbox_dev *mdev = &mbox->dev[devid]; in otx2_mbox_reset()
41 __otx2_mbox_reset(mbox, devid); in otx2_mbox_reset()
46 void otx2_mbox_destroy(struct otx2_mbox *mbox) in otx2_mbox_destroy() argument
48 mbox->reg_base = NULL; in otx2_mbox_destroy()
[all …]
/kernel/linux/linux-5.10/drivers/mailbox/
Dmailbox-altera.c60 static inline int altera_mbox_full(struct altera_mbox *mbox) in altera_mbox_full() argument
64 status = readl_relaxed(mbox->mbox_base + MAILBOX_STS_REG); in altera_mbox_full()
68 static inline int altera_mbox_pending(struct altera_mbox *mbox) in altera_mbox_pending() argument
72 status = readl_relaxed(mbox->mbox_base + MAILBOX_STS_REG); in altera_mbox_pending()
76 static void altera_mbox_rx_intmask(struct altera_mbox *mbox, bool enable) in altera_mbox_rx_intmask() argument
80 mask = readl_relaxed(mbox->mbox_base + MAILBOX_INTMASK_REG); in altera_mbox_rx_intmask()
85 writel_relaxed(mask, mbox->mbox_base + MAILBOX_INTMASK_REG); in altera_mbox_rx_intmask()
88 static void altera_mbox_tx_intmask(struct altera_mbox *mbox, bool enable) in altera_mbox_tx_intmask() argument
92 mask = readl_relaxed(mbox->mbox_base + MAILBOX_INTMASK_REG); in altera_mbox_tx_intmask()
97 writel_relaxed(mask, mbox->mbox_base + MAILBOX_INTMASK_REG); in altera_mbox_tx_intmask()
[all …]
Dhi6220-mailbox.c89 static void mbox_set_state(struct hi6220_mbox *mbox, in mbox_set_state() argument
94 status = readl(mbox->base + MBOX_MODE_REG(slot)); in mbox_set_state()
96 writel(status, mbox->base + MBOX_MODE_REG(slot)); in mbox_set_state()
99 static void mbox_set_mode(struct hi6220_mbox *mbox, in mbox_set_mode() argument
104 mode = readl(mbox->base + MBOX_MODE_REG(slot)); in mbox_set_mode()
106 writel(mode, mbox->base + MBOX_MODE_REG(slot)); in mbox_set_mode()
112 struct hi6220_mbox *mbox = mchan->parent; in hi6220_mbox_last_tx_done() local
116 BUG_ON(mbox->tx_irq_mode); in hi6220_mbox_last_tx_done()
118 state = readl(mbox->base + MBOX_MODE_REG(mchan->slot)); in hi6220_mbox_last_tx_done()
125 struct hi6220_mbox *mbox = mchan->parent; in hi6220_mbox_send_data() local
[all …]
Domap-mailbox.c68 struct omap_mbox *mbox; member
144 static u32 mbox_fifo_read(struct omap_mbox *mbox) in mbox_fifo_read() argument
146 struct omap_mbox_fifo *fifo = &mbox->rx_fifo; in mbox_fifo_read()
148 return mbox_read_reg(mbox->parent, fifo->msg); in mbox_fifo_read()
151 static void mbox_fifo_write(struct omap_mbox *mbox, u32 msg) in mbox_fifo_write() argument
153 struct omap_mbox_fifo *fifo = &mbox->tx_fifo; in mbox_fifo_write()
155 mbox_write_reg(mbox->parent, msg, fifo->msg); in mbox_fifo_write()
158 static int mbox_fifo_empty(struct omap_mbox *mbox) in mbox_fifo_empty() argument
160 struct omap_mbox_fifo *fifo = &mbox->rx_fifo; in mbox_fifo_empty()
162 return (mbox_read_reg(mbox->parent, fifo->msg_stat) == 0); in mbox_fifo_empty()
[all …]
Dsun6i-msgbox.c44 #define mbox_dbg(mbox, ...) dev_dbg((mbox)->controller.dev, __VA_ARGS__) argument
58 return chan - chan->mbox->chans; in channel_number()
68 struct sun6i_msgbox *mbox = dev_id; in sun6i_msgbox_irq() local
73 status = readl(mbox->regs + LOCAL_IRQ_EN_REG) & in sun6i_msgbox_irq()
74 readl(mbox->regs + LOCAL_IRQ_STAT_REG); in sun6i_msgbox_irq()
80 struct mbox_chan *chan = &mbox->controller.chans[n]; in sun6i_msgbox_irq()
86 uint32_t msg = readl(mbox->regs + MSG_DATA_REG(n)); in sun6i_msgbox_irq()
88 mbox_dbg(mbox, "Channel %d received 0x%08x\n", n, msg); in sun6i_msgbox_irq()
93 writel(RX_IRQ(n), mbox->regs + LOCAL_IRQ_STAT_REG); in sun6i_msgbox_irq()
101 struct sun6i_msgbox *mbox = to_sun6i_msgbox(chan); in sun6i_msgbox_send_data() local
[all …]
Darmada-37xx-rwtm-mailbox.c45 struct a37xx_mbox *mbox = chan->con_priv; in a37xx_mbox_receive() local
49 rx_msg.retval = readl(mbox->base + RWTM_MBOX_RETURN_STATUS); in a37xx_mbox_receive()
51 rx_msg.status[i] = readl(mbox->base + RWTM_MBOX_STATUS(i)); in a37xx_mbox_receive()
59 struct a37xx_mbox *mbox = chan->con_priv; in a37xx_mbox_irq_handler() local
62 reg = readl(mbox->base + RWTM_HOST_INT_RESET); in a37xx_mbox_irq_handler()
68 dev_err(mbox->dev, "Secure processor command queue full\n"); in a37xx_mbox_irq_handler()
70 writel(reg, mbox->base + RWTM_HOST_INT_RESET); in a37xx_mbox_irq_handler()
79 struct a37xx_mbox *mbox = chan->con_priv; in a37xx_mbox_send_data() local
87 reg = readl(mbox->base + RWTM_MBOX_FIFO_STATUS); in a37xx_mbox_send_data()
89 dev_warn(mbox->dev, "Secure processor not ready\n"); in a37xx_mbox_send_data()
[all …]
Dbcm2835-mailbox.c63 return container_of(link->mbox, struct bcm2835_mbox, controller); in bcm2835_link_mbox()
68 struct bcm2835_mbox *mbox = dev_id; in bcm2835_mbox_irq() local
69 struct device *dev = mbox->controller.dev; in bcm2835_mbox_irq()
70 struct mbox_chan *link = &mbox->controller.chans[0]; in bcm2835_mbox_irq()
72 while (!(readl(mbox->regs + MAIL0_STA) & ARM_MS_EMPTY)) { in bcm2835_mbox_irq()
73 u32 msg = readl(mbox->regs + MAIL0_RD); in bcm2835_mbox_irq()
82 struct bcm2835_mbox *mbox = bcm2835_link_mbox(link); in bcm2835_send_data() local
85 spin_lock(&mbox->lock); in bcm2835_send_data()
86 writel(msg, mbox->regs + MAIL1_WRT); in bcm2835_send_data()
87 dev_dbg(mbox->controller.dev, "Request 0x%08X\n", msg); in bcm2835_send_data()
[all …]
Dhi3660-mailbox.c24 #define MBOX_BASE(mbox, ch) ((mbox)->base + ((ch) * 0x40)) argument
81 static struct hi3660_mbox *to_hi3660_mbox(struct mbox_controller *mbox) in to_hi3660_mbox() argument
83 return container_of(mbox, struct hi3660_mbox, controller); in to_hi3660_mbox()
89 struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox); in hi3660_mbox_check_state() local
90 struct hi3660_chan_info *mchan = &mbox->mchan[ch]; in hi3660_mbox_check_state()
91 void __iomem *base = MBOX_BASE(mbox, ch); in hi3660_mbox_check_state()
103 dev_err(mbox->dev, "%s: timeout for receiving ack\n", __func__); in hi3660_mbox_check_state()
115 struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox); in hi3660_mbox_unlock() local
119 writel(MBOX_IPC_UNLOCK, mbox->base + MBOX_IPC_LOCK_REG); in hi3660_mbox_unlock()
121 val = readl(mbox->base + MBOX_IPC_LOCK_REG); in hi3660_mbox_unlock()
[all …]
/kernel/linux/linux-6.6/drivers/mailbox/
Dmailbox-altera.c60 static inline int altera_mbox_full(struct altera_mbox *mbox) in altera_mbox_full() argument
64 status = readl_relaxed(mbox->mbox_base + MAILBOX_STS_REG); in altera_mbox_full()
68 static inline int altera_mbox_pending(struct altera_mbox *mbox) in altera_mbox_pending() argument
72 status = readl_relaxed(mbox->mbox_base + MAILBOX_STS_REG); in altera_mbox_pending()
76 static void altera_mbox_rx_intmask(struct altera_mbox *mbox, bool enable) in altera_mbox_rx_intmask() argument
80 mask = readl_relaxed(mbox->mbox_base + MAILBOX_INTMASK_REG); in altera_mbox_rx_intmask()
85 writel_relaxed(mask, mbox->mbox_base + MAILBOX_INTMASK_REG); in altera_mbox_rx_intmask()
88 static void altera_mbox_tx_intmask(struct altera_mbox *mbox, bool enable) in altera_mbox_tx_intmask() argument
92 mask = readl_relaxed(mbox->mbox_base + MAILBOX_INTMASK_REG); in altera_mbox_tx_intmask()
97 writel_relaxed(mask, mbox->mbox_base + MAILBOX_INTMASK_REG); in altera_mbox_tx_intmask()
[all …]
Dhi6220-mailbox.c90 static void mbox_set_state(struct hi6220_mbox *mbox, in mbox_set_state() argument
95 status = readl(mbox->base + MBOX_MODE_REG(slot)); in mbox_set_state()
97 writel(status, mbox->base + MBOX_MODE_REG(slot)); in mbox_set_state()
100 static void mbox_set_mode(struct hi6220_mbox *mbox, in mbox_set_mode() argument
105 mode = readl(mbox->base + MBOX_MODE_REG(slot)); in mbox_set_mode()
107 writel(mode, mbox->base + MBOX_MODE_REG(slot)); in mbox_set_mode()
113 struct hi6220_mbox *mbox = mchan->parent; in hi6220_mbox_last_tx_done() local
117 BUG_ON(mbox->tx_irq_mode); in hi6220_mbox_last_tx_done()
119 state = readl(mbox->base + MBOX_MODE_REG(mchan->slot)); in hi6220_mbox_last_tx_done()
126 struct hi6220_mbox *mbox = mchan->parent; in hi6220_mbox_send_data() local
[all …]
Domap-mailbox.c68 struct omap_mbox *mbox; member
144 static u32 mbox_fifo_read(struct omap_mbox *mbox) in mbox_fifo_read() argument
146 struct omap_mbox_fifo *fifo = &mbox->rx_fifo; in mbox_fifo_read()
148 return mbox_read_reg(mbox->parent, fifo->msg); in mbox_fifo_read()
151 static void mbox_fifo_write(struct omap_mbox *mbox, u32 msg) in mbox_fifo_write() argument
153 struct omap_mbox_fifo *fifo = &mbox->tx_fifo; in mbox_fifo_write()
155 mbox_write_reg(mbox->parent, msg, fifo->msg); in mbox_fifo_write()
158 static int mbox_fifo_empty(struct omap_mbox *mbox) in mbox_fifo_empty() argument
160 struct omap_mbox_fifo *fifo = &mbox->rx_fifo; in mbox_fifo_empty()
162 return (mbox_read_reg(mbox->parent, fifo->msg_stat) == 0); in mbox_fifo_empty()
[all …]
Dmailbox-mpfs.c74 static bool mpfs_mbox_busy(struct mpfs_mbox *mbox) in mpfs_mbox_busy() argument
78 status = readl_relaxed(mbox->ctrl_base + SERVICES_SR_OFFSET); in mpfs_mbox_busy()
85 struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv; in mpfs_mbox_last_tx_done() local
86 struct mpfs_mss_response *response = mbox->response; in mpfs_mbox_last_tx_done()
89 if (mpfs_mbox_busy(mbox)) in mpfs_mbox_last_tx_done()
98 val = readl_relaxed(mbox->ctrl_base + SERVICES_SR_OFFSET); in mpfs_mbox_last_tx_done()
106 struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv; in mpfs_mbox_send_data() local
112 mbox->response = msg->response; in mpfs_mbox_send_data()
113 mbox->resp_offset = msg->resp_offset; in mpfs_mbox_send_data()
115 if (mpfs_mbox_busy(mbox)) in mpfs_mbox_send_data()
[all …]
Dsun6i-msgbox.c44 #define mbox_dbg(mbox, ...) dev_dbg((mbox)->controller.dev, __VA_ARGS__) argument
58 return chan - chan->mbox->chans; in channel_number()
68 struct sun6i_msgbox *mbox = dev_id; in sun6i_msgbox_irq() local
73 status = readl(mbox->regs + LOCAL_IRQ_EN_REG) & in sun6i_msgbox_irq()
74 readl(mbox->regs + LOCAL_IRQ_STAT_REG); in sun6i_msgbox_irq()
80 struct mbox_chan *chan = &mbox->controller.chans[n]; in sun6i_msgbox_irq()
86 uint32_t msg = readl(mbox->regs + MSG_DATA_REG(n)); in sun6i_msgbox_irq()
88 mbox_dbg(mbox, "Channel %d received 0x%08x\n", n, msg); in sun6i_msgbox_irq()
93 writel(RX_IRQ(n), mbox->regs + LOCAL_IRQ_STAT_REG); in sun6i_msgbox_irq()
101 struct sun6i_msgbox *mbox = to_sun6i_msgbox(chan); in sun6i_msgbox_send_data() local
[all …]
Darmada-37xx-rwtm-mailbox.c45 struct a37xx_mbox *mbox = chan->con_priv; in a37xx_mbox_receive() local
49 rx_msg.retval = readl(mbox->base + RWTM_MBOX_RETURN_STATUS); in a37xx_mbox_receive()
51 rx_msg.status[i] = readl(mbox->base + RWTM_MBOX_STATUS(i)); in a37xx_mbox_receive()
59 struct a37xx_mbox *mbox = chan->con_priv; in a37xx_mbox_irq_handler() local
62 reg = readl(mbox->base + RWTM_HOST_INT_RESET); in a37xx_mbox_irq_handler()
68 dev_err(mbox->dev, "Secure processor command queue full\n"); in a37xx_mbox_irq_handler()
70 writel(reg, mbox->base + RWTM_HOST_INT_RESET); in a37xx_mbox_irq_handler()
79 struct a37xx_mbox *mbox = chan->con_priv; in a37xx_mbox_send_data() local
87 reg = readl(mbox->base + RWTM_MBOX_FIFO_STATUS); in a37xx_mbox_send_data()
89 dev_warn(mbox->dev, "Secure processor not ready\n"); in a37xx_mbox_send_data()
[all …]
Dbcm2835-mailbox.c63 return container_of(link->mbox, struct bcm2835_mbox, controller); in bcm2835_link_mbox()
68 struct bcm2835_mbox *mbox = dev_id; in bcm2835_mbox_irq() local
69 struct device *dev = mbox->controller.dev; in bcm2835_mbox_irq()
70 struct mbox_chan *link = &mbox->controller.chans[0]; in bcm2835_mbox_irq()
72 while (!(readl(mbox->regs + MAIL0_STA) & ARM_MS_EMPTY)) { in bcm2835_mbox_irq()
73 u32 msg = readl(mbox->regs + MAIL0_RD); in bcm2835_mbox_irq()
82 struct bcm2835_mbox *mbox = bcm2835_link_mbox(link); in bcm2835_send_data() local
85 spin_lock(&mbox->lock); in bcm2835_send_data()
86 writel(msg, mbox->regs + MAIL1_WRT); in bcm2835_send_data()
87 dev_dbg(mbox->controller.dev, "Request 0x%08X\n", msg); in bcm2835_send_data()
[all …]
Dhi3660-mailbox.c25 #define MBOX_BASE(mbox, ch) ((mbox)->base + ((ch) * 0x40)) argument
80 static struct hi3660_mbox *to_hi3660_mbox(struct mbox_controller *mbox) in to_hi3660_mbox() argument
82 return container_of(mbox, struct hi3660_mbox, controller); in to_hi3660_mbox()
88 struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox); in hi3660_mbox_check_state() local
89 struct hi3660_chan_info *mchan = &mbox->mchan[ch]; in hi3660_mbox_check_state()
90 void __iomem *base = MBOX_BASE(mbox, ch); in hi3660_mbox_check_state()
102 dev_err(mbox->dev, "%s: timeout for receiving ack\n", __func__); in hi3660_mbox_check_state()
114 struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox); in hi3660_mbox_unlock() local
118 writel(MBOX_IPC_UNLOCK, mbox->base + MBOX_IPC_LOCK_REG); in hi3660_mbox_unlock()
120 val = readl(mbox->base + MBOX_IPC_LOCK_REG); in hi3660_mbox_unlock()
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/marvell/octeontx2/af/
Dmbox.c16 #include "mbox.h"
21 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid) in __otx2_mbox_reset() argument
23 void *hw_mbase = mbox->hwbase + (devid * MBOX_SIZE); in __otx2_mbox_reset()
24 struct otx2_mbox_dev *mdev = &mbox->dev[devid]; in __otx2_mbox_reset()
27 tx_hdr = hw_mbase + mbox->tx_start; in __otx2_mbox_reset()
28 rx_hdr = hw_mbase + mbox->rx_start; in __otx2_mbox_reset()
39 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid) in otx2_mbox_reset() argument
41 struct otx2_mbox_dev *mdev = &mbox->dev[devid]; in otx2_mbox_reset()
44 __otx2_mbox_reset(mbox, devid); in otx2_mbox_reset()
49 void otx2_mbox_destroy(struct otx2_mbox *mbox) in otx2_mbox_destroy() argument
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/marvell/octeon_ep/
Doctep_ctrl_mbox.c27 /* Size of mbox info in bytes */
29 /* Size of mbox host to fw queue info in bytes */
31 /* Size of mbox fw to host queue info in bytes */
74 int octep_ctrl_mbox_init(struct octep_ctrl_mbox *mbox) in octep_ctrl_mbox_init() argument
78 if (!mbox) in octep_ctrl_mbox_init()
81 if (!mbox->barmem) { in octep_ctrl_mbox_init()
82 pr_info("octep_ctrl_mbox : Invalid barmem %p\n", mbox->barmem); in octep_ctrl_mbox_init()
86 magic_num = readq(OCTEP_CTRL_MBOX_INFO_MAGIC_NUM(mbox->barmem)); in octep_ctrl_mbox_init()
92 status = readq(OCTEP_CTRL_MBOX_INFO_FW_STATUS(mbox->barmem)); in octep_ctrl_mbox_init()
98 fw_versions = readq(OCTEP_CTRL_MBOX_INFO_FW_VERSION(mbox->barmem)); in octep_ctrl_mbox_init()
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/marvell/octeontx2/nic/
Dotx2_dmac_flt.c17 mutex_lock(&pf->mbox.lock); in otx2_dmacflt_do_add()
19 req = otx2_mbox_alloc_msg_cgx_mac_addr_add(&pf->mbox); in otx2_dmacflt_do_add()
21 mutex_unlock(&pf->mbox.lock); in otx2_dmacflt_do_add()
26 err = otx2_sync_mbox_msg(&pf->mbox); in otx2_dmacflt_do_add()
30 otx2_mbox_get_rsp(&pf->mbox.mbox, 0, &req->hdr); in otx2_dmacflt_do_add()
32 mutex_unlock(&pf->mbox.lock); in otx2_dmacflt_do_add()
39 mutex_unlock(&pf->mbox.lock); in otx2_dmacflt_do_add()
49 mutex_lock(&pf->mbox.lock); in otx2_dmacflt_add_pfmac()
51 req = otx2_mbox_alloc_msg_cgx_mac_addr_set(&pf->mbox); in otx2_dmacflt_add_pfmac()
53 mutex_unlock(&pf->mbox.lock); in otx2_dmacflt_add_pfmac()
[all …]
/kernel/linux/linux-6.6/drivers/crypto/marvell/octeontx2/
Dotx2_cpt_mbox_common.c7 int otx2_cpt_send_mbox_msg(struct otx2_mbox *mbox, struct pci_dev *pdev) in otx2_cpt_send_mbox_msg() argument
11 otx2_mbox_msg_send(mbox, 0); in otx2_cpt_send_mbox_msg()
12 ret = otx2_mbox_wait_for_rsp(mbox, 0); in otx2_cpt_send_mbox_msg()
14 dev_err(&pdev->dev, "RVU MBOX timeout.\n"); in otx2_cpt_send_mbox_msg()
17 dev_err(&pdev->dev, "RVU MBOX error: %d.\n", ret); in otx2_cpt_send_mbox_msg()
24 int otx2_cpt_send_ready_msg(struct otx2_mbox *mbox, struct pci_dev *pdev) in otx2_cpt_send_ready_msg() argument
28 req = otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req), in otx2_cpt_send_ready_msg()
31 dev_err(&pdev->dev, "RVU MBOX failed to get message.\n"); in otx2_cpt_send_ready_msg()
38 return otx2_cpt_send_mbox_msg(mbox, pdev); in otx2_cpt_send_ready_msg()
42 int otx2_cpt_send_af_reg_requests(struct otx2_mbox *mbox, struct pci_dev *pdev) in otx2_cpt_send_af_reg_requests() argument
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mailbox/
Dti,omap-mailbox.yaml56 "mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt
60 The equivalent "mbox-names" property value can be used to give a name to the
64 omap-mbox-descriptor:
67 The omap-mbox-descriptor is made of up of 3 cells and represents a single
72 mailbox fifo id used either for transmitting on ti,mbox-tx channel or
73 for receiving on ti,mbox-rx channel (fifo_id). This is the hardware
96 ti,mbox-tx:
97 $ref: "#/$defs/omap-mbox-descriptor"
100 ti,mbox-rx:
101 $ref: "#/$defs/omap-mbox-descriptor"
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/marvell/octeontx2/nic/
Dotx2_common.h20 #include <mbox.h>
143 struct mbox { struct
144 struct otx2_mbox mbox; argument
149 void *bbuf_base; /* Bounce buffer for mbox memory */ argument
151 int num_msgs; /* mbox number of messages */ argument
248 /* Mbox */
249 struct mbox mbox; member
250 struct mbox *mbox_pfvf;
356 /* Mbox bounce buffer APIs */
357 static inline int otx2_mbox_bbuf_init(struct mbox *mbox, struct pci_dev *pdev) in otx2_mbox_bbuf_init() argument
[all …]
Dotx2_vf.c35 "Mbox msg with unknown ID %d\n", msg->id); in otx2vf_process_vfaf_mbox_msg()
41 "Mbox msg with wrong signature %x, ID %d\n", in otx2vf_process_vfaf_mbox_msg()
76 "Mbox msg response has err %d, ID %d\n", in otx2vf_process_vfaf_mbox_msg()
86 struct otx2_mbox *mbox; in otx2vf_vfaf_mbox_handler() local
87 struct mbox *af_mbox; in otx2vf_vfaf_mbox_handler()
90 af_mbox = container_of(work, struct mbox, mbox_wrk); in otx2vf_vfaf_mbox_handler()
91 mbox = &af_mbox->mbox; in otx2vf_vfaf_mbox_handler()
92 mdev = &mbox->dev[0]; in otx2vf_vfaf_mbox_handler()
93 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); in otx2vf_vfaf_mbox_handler()
96 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); in otx2vf_vfaf_mbox_handler()
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