| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/ |
| D | ste-dma40.txt | 4 - compatible: "stericsson,dma40"
5 - reg: Address range of the DMAC registers
6 - reg-names: Names of the above areas to use during resource look-up
7 - interrupt: Should contain the DMAC interrupt number
8 - #dma-cells: must be <3>
9 - memcpy-channels: Channels to be used for memcpy
12 - dma-channels: Number of channels supported by hardware - if not present
14 - disabled-channels: Channels which can not be used
18 dma: dma-controller@801c0000 {
19 compatible = "stericsson,db8500-dma40", "stericsson,dma40";
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| D | ti-edma.txt | 8 ------------------------------------------------------------------------------
12 --------------------
13 - compatible: Should be:
14 - "ti,edma3-tpcc" for the channel controller(s) on OMAP,
16 - "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the
18 - #dma-cells: Should be set to <2>. The first number is the DMA request
20 - reg: Memory map of eDMA CC
21 - reg-names: "edma3_cc"
22 - interrupts: Interrupt lines for CCINT, MPERR and CCERRINT.
23 - interrupt-names: "edma3_ccint", "edma3_mperr" and "edma3_ccerrint"
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| D | arm-pl08x.txt | 4 - compatible: "arm,pl080", "arm,primecell";
7 - arm,primecell-periphid: on the FTDMAC020 the primecell ID is not hard-coded
11 - reg: Address range of the PL08x registers
12 - interrupt: The PL08x interrupt number
13 - clocks: The clock running the IP core clock
14 - clock-names: Must contain "apb_pclk"
15 - lli-bus-interface-ahb1: if AHB master 1 is eligible for fetching LLIs
16 - lli-bus-interface-ahb2: if AHB master 2 is eligible for fetching LLIs
17 - mem-bus-interface-ahb1: if AHB master 1 is eligible for fetching memory contents
18 - mem-bus-interface-ahb2: if AHB master 2 is eligible for fetching memory contents
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| D | qcom_hidma_mgmt.txt | 4 memcpy and memset capabilities. It has been designed for virtualized
7 Each HIDMA HW instance consists of multiple DMA channels. These channels
9 among channels based on the priority and weight assignments.
18 - compatible: "qcom,hidma-mgmt-1.0";
19 - reg: Address range for DMA device
20 - dma-channels: Number of channels supported by this DMA controller.
21 - max-write-burst-bytes: Maximum write burst in bytes that HIDMA can
22 occupy the bus for in a single transaction. A memcpy requested is
26 - max-read-burst-bytes: Maximum read burst in bytes that HIDMA can
27 occupy the bus for in a single transaction. A memcpy request is
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| /kernel/linux/linux-5.10/drivers/dma/ |
| D | s3c24xx-dma.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * based on amba-pl08x.c
10 * Copyright (c) 2010 ST-Ericsson SA
16 * that can be routed to any of the 4 to 8 hardware-channels.
18 * Therefore on these DMA controllers the number of channels
24 * - bursts
30 #include <linux/dma-mapping.h>
36 #include <linux/platform_data/dma-s3c24xx.h>
39 #include "virt-dma.h"
95 * for a DMA source. Instead only specific channels are valid.
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| D | amba-pl08x.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (c) 2010 ST-Ericsson SA
17 * The PL080 has 8 channels available for simultaneous use, and the PL081
18 * has only two channels. So on these DMA controllers the number of channels
27 * - CH_CONFIG register at different offset,
28 * - separate CH_CONTROL2 register for transfer size,
29 * - bigger maximum transfer size,
30 * - 8-word aligned LLI, instead of 4-word, due to extra CCTL2 word,
31 * - no support for peripheral flow control.
45 * (Bursts are irrelevant for mem to mem transfers - there are no burst
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/dma/ |
| D | stericsson,dma40.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linus.walleij@linaro.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
32 10: Multi-Channel Display Engine MCDE RX
73 51: memcpy TX (to be used by the DMA driver for memcpy operations)
78 56: memcpy (to be used by the DMA driver for memcpy operations)
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| D | ti-edma.txt | 8 ------------------------------------------------------------------------------
12 --------------------
13 - compatible: Should be:
14 - "ti,edma3-tpcc" for the channel controller(s) on OMAP,
16 - "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the
18 - #dma-cells: Should be set to <2>. The first number is the DMA request
20 - reg: Memory map of eDMA CC
21 - reg-names: "edma3_cc"
22 - interrupts: Interrupt lines for CCINT, MPERR and CCERRINT.
23 - interrupt-names: "edma3_ccint", "edma3_mperr" and "edma3_ccerrint"
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| D | qcom_hidma_mgmt.txt | 4 memcpy and memset capabilities. It has been designed for virtualized
7 Each HIDMA HW instance consists of multiple DMA channels. These channels
9 among channels based on the priority and weight assignments.
18 - compatible: "qcom,hidma-mgmt-1.0";
19 - reg: Address range for DMA device
20 - dma-channels: Number of channels supported by this DMA controller.
21 - max-write-burst-bytes: Maximum write burst in bytes that HIDMA can
22 occupy the bus for in a single transaction. A memcpy requested is
26 - max-read-burst-bytes: Maximum read burst in bytes that HIDMA can
27 occupy the bus for in a single transaction. A memcpy request is
[all …]
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| /kernel/linux/linux-6.6/drivers/net/wireless/ti/wl12xx/ |
| D | scan.c | 1 // SPDX-License-Identifier: GPL-2.0-only
15 struct basic_scan_channel_params *channels, in wl1271_get_scan_channels() argument
18 struct conf_scan_settings *c = &wl->conf.scan; in wl1271_get_scan_channels()
23 i < req->n_channels && j < WL1271_SCAN_MAX_CHANNELS; in wl1271_get_scan_channels()
25 flags = req->channels[i]->flags; in wl1271_get_scan_channels()
27 if (!test_bit(i, wl->scan.scanned_ch) && in wl1271_get_scan_channels()
29 (req->channels[i]->band == band) && in wl1271_get_scan_channels()
32 * channels, even if not marked as such. in wl1271_get_scan_channels()
33 * In active scans, we only scan channels not in wl1271_get_scan_channels()
38 req->channels[i]->band, in wl1271_get_scan_channels()
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| /kernel/linux/linux-5.10/drivers/net/wireless/ti/wl12xx/ |
| D | scan.c | 1 // SPDX-License-Identifier: GPL-2.0-only
15 struct basic_scan_channel_params *channels, in wl1271_get_scan_channels() argument
18 struct conf_scan_settings *c = &wl->conf.scan; in wl1271_get_scan_channels()
23 i < req->n_channels && j < WL1271_SCAN_MAX_CHANNELS; in wl1271_get_scan_channels()
25 flags = req->channels[i]->flags; in wl1271_get_scan_channels()
27 if (!test_bit(i, wl->scan.scanned_ch) && in wl1271_get_scan_channels()
29 (req->channels[i]->band == band) && in wl1271_get_scan_channels()
32 * channels, even if not marked as such. in wl1271_get_scan_channels()
33 * In active scans, we only scan channels not in wl1271_get_scan_channels()
38 req->channels[i]->band, in wl1271_get_scan_channels()
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| /kernel/linux/linux-6.6/drivers/dma/ |
| D | amba-pl08x.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (c) 2010 ST-Ericsson SA
17 * The PL080 has 8 channels available for simultaneous use, and the PL081
18 * has only two channels. So on these DMA controllers the number of channels
27 * - CH_CONFIG register at different offset,
28 * - separate CH_CONTROL2 register for transfer size,
29 * - bigger maximum transfer size,
30 * - 8-word aligned LLI, instead of 4-word, due to extra CCTL2 word,
31 * - no support for peripheral flow control.
45 * (Bursts are irrelevant for mem to mem transfers - there are no burst
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| /kernel/linux/linux-6.6/include/linux/amba/ |
| D | pl08x.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/amba/pl08x.h - ARM PrimeCell DMA Controller driver
6 * Copyright (C) 2010 ST-Ericsson SA
32 * struct pl08x_channel_data - data structure to pass info between
84 * struct pl08x_platform_data - the platform configuration for the PL08x
86 * @slave_channels: the channels defined for the different devices on the
87 * platform, all inclusive, including multiplexed channels. The available
88 * physical channels will be multiplexed around these signals as they are
89 * requested, just enumerate all possible channels.
91 * @memcpy_burst_size: the appropriate burst size for memcpy operations
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| /kernel/linux/linux-5.10/include/linux/amba/ |
| D | pl08x.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/amba/pl08x.h - ARM PrimeCell DMA Controller driver
6 * Copyright (C) 2010 ST-Ericsson SA
32 * struct pl08x_channel_data - data structure to pass info between
84 * struct pl08x_platform_data - the platform configuration for the PL08x
86 * @slave_channels: the channels defined for the different devices on the
87 * platform, all inclusive, including multiplexed channels. The available
88 * physical channels will be multiplexed around these signals as they are
89 * requested, just enumerate all possible channels.
91 * @memcpy_burst_size: the appropriate burst size for memcpy operations
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| /kernel/linux/linux-5.10/include/linux/platform_data/ |
| D | dma-ste-dma40.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) ST-Ericsson SA 2007-2010
4 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
5 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
20 * Size is in the units of addr-widths (1,2,4,8 bytes)
25 /* dev types for memcpy */
26 #define STEDMA40_DEV_DST_MEMORY (-1)
27 #define STEDMA40_DEV_SRC_MEMORY (-1)
49 /* The value 4 indicates that PEN-reg shall be set to 0 */
65 /* Maximum number of possible physical channels */
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| D | dma-ep93xx.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/dma-mapping.h>
10 * M2P channels.
25 /* M2M channels */
30 * struct ep93xx_dma_data - configuration data for the EP93xx dmaengine
36 * function. Note that this is only needed for slave/cyclic channels. For
37 * memcpy channels %NULL data should be passed.
46 * struct ep93xx_dma_chan_data - platform specific data for a DMA channel
58 * struct ep93xx_dma_platform_data - platform data for the dmaengine driver
59 * @channels: array of channels which are passed to the driver
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| /kernel/linux/linux-5.10/drivers/net/wireless/ti/wlcore/ |
| D | scan.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2009-2010 Nokia Corporation
35 mutex_lock(&wl->mutex); in wl1271_scan_complete_work()
37 if (unlikely(wl->state != WLCORE_STATE_ON)) in wl1271_scan_complete_work()
40 if (wl->scan.state == WL1271_SCAN_STATE_IDLE) in wl1271_scan_complete_work()
43 wlvif = wl->scan_wlvif; in wl1271_scan_complete_work()
47 * prevents just-finished scans from triggering the watchdog in wl1271_scan_complete_work()
51 wl->scan.state = WL1271_SCAN_STATE_IDLE; in wl1271_scan_complete_work()
52 memset(wl->scan.scanned_ch, 0, sizeof(wl->scan.scanned_ch)); in wl1271_scan_complete_work()
53 wl->scan.req = NULL; in wl1271_scan_complete_work()
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| /kernel/linux/linux-6.6/drivers/net/wireless/ti/wlcore/ |
| D | scan.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2009-2010 Nokia Corporation
35 mutex_lock(&wl->mutex); in wl1271_scan_complete_work()
37 if (unlikely(wl->state != WLCORE_STATE_ON)) in wl1271_scan_complete_work()
40 if (wl->scan.state == WL1271_SCAN_STATE_IDLE) in wl1271_scan_complete_work()
43 wlvif = wl->scan_wlvif; in wl1271_scan_complete_work()
47 * prevents just-finished scans from triggering the watchdog in wl1271_scan_complete_work()
51 wl->scan.state = WL1271_SCAN_STATE_IDLE; in wl1271_scan_complete_work()
52 memset(wl->scan.scanned_ch, 0, sizeof(wl->scan.scanned_ch)); in wl1271_scan_complete_work()
53 wl->scan.req = NULL; in wl1271_scan_complete_work()
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| /kernel/linux/linux-6.6/drivers/media/pci/tw686x/ |
| D | tw686x-core.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 VanguardiaSur - www.vanguardiasur.com.ar
10 * -----
12 * 1. Under stress-testing, it has been observed that the PCIe link
14 * to allow device hot-unplugging.
17 * including: scatter-gather, field and frame modes. However,
22 * Therefore, driver implements a dma_mode called 'memcpy' which
28 * a timer to limit the rate at which DMA is reset on DMA channels error.
41 #include "tw686x-regs.h"
50 * users wanting fine-grain control over the interrupt rate should
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| /kernel/linux/linux-5.10/drivers/media/pci/tw686x/ |
| D | tw686x-core.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 VanguardiaSur - www.vanguardiasur.com.ar
10 * -----
12 * 1. Under stress-testing, it has been observed that the PCIe link
14 * to allow device hot-unplugging.
17 * including: scatter-gather, field and frame modes. However,
22 * Therefore, driver implements a dma_mode called 'memcpy' which
28 * a timer to limit the rate at which DMA is reset on DMA channels error.
41 #include "tw686x-regs.h"
50 * users wanting fine-grain control over the interrupt rate should
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| /kernel/linux/linux-6.6/drivers/net/wireless/ti/wl1251/ |
| D | cmd.c | 1 // SPDX-License-Identifier: GPL-2.0
15 * wl1251_cmd_send - Send command to firmware
30 cmd->id = id; in wl1251_cmd_send()
31 cmd->status = 0; in wl1251_cmd_send()
35 wl1251_mem_write(wl, wl->cmd_box_addr, buf, len); in wl1251_cmd_send()
45 ret = -ETIMEDOUT; in wl1251_cmd_send()
62 * wl1251_cmd_test - Send test command to firmware
90 wl1251_mem_read(wl, wl->cmd_box_addr, buf, buf_len); in wl1251_cmd_test()
94 if (cmd_answer->header.status != CMD_STATUS_SUCCESS) in wl1251_cmd_test()
96 cmd_answer->header.status); in wl1251_cmd_test()
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| /kernel/linux/linux-5.10/drivers/net/wireless/ti/wl1251/ |
| D | cmd.c | 1 // SPDX-License-Identifier: GPL-2.0
30 cmd->id = id; in wl1251_cmd_send()
31 cmd->status = 0; in wl1251_cmd_send()
35 wl1251_mem_write(wl, wl->cmd_box_addr, buf, len); in wl1251_cmd_send()
45 ret = -ETIMEDOUT; in wl1251_cmd_send()
90 wl1251_mem_read(wl, wl->cmd_box_addr, buf, buf_len); in wl1251_cmd_test()
94 if (cmd_answer->header.status != CMD_STATUS_SUCCESS) in wl1251_cmd_test()
96 cmd_answer->header.status); in wl1251_cmd_test()
117 acx->id = id; in wl1251_cmd_interrogate()
120 acx->len = len - sizeof(*acx); in wl1251_cmd_interrogate()
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| /kernel/linux/linux-6.6/drivers/net/netdevsim/ |
| D | ethtool.c | 1 // SPDX-License-Identifier: GPL-2.0
16 if (ns->ethtool.pauseparam.report_stats_rx) in nsim_get_pause_stats()
17 pause_stats->rx_pause_frames = 1; in nsim_get_pause_stats()
18 if (ns->ethtool.pauseparam.report_stats_tx) in nsim_get_pause_stats()
19 pause_stats->tx_pause_frames = 2; in nsim_get_pause_stats()
27 pause->autoneg = 0; /* We don't support ksettings, so can't pretend */ in nsim_get_pauseparam()
28 pause->rx_pause = ns->ethtool.pauseparam.rx; in nsim_get_pauseparam()
29 pause->tx_pause = ns->ethtool.pauseparam.tx; in nsim_get_pauseparam()
37 if (pause->autoneg) in nsim_set_pauseparam()
38 return -EINVAL; in nsim_set_pauseparam()
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| /kernel/linux/linux-6.6/include/linux/platform_data/ |
| D | dma-ep93xx.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/dma-mapping.h>
10 * M2P channels.
25 /* M2M channels */
30 * struct ep93xx_dma_data - configuration data for the EP93xx dmaengine
36 * function. Note that this is only needed for slave/cyclic channels. For
37 * memcpy channels %NULL data should be passed.
46 * struct ep93xx_dma_chan_data - platform specific data for a DMA channel
58 * struct ep93xx_dma_platform_data - platform data for the dmaengine driver
59 * @channels: array of channels which are passed to the driver
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| /kernel/linux/linux-6.6/drivers/staging/greybus/ |
| D | audio_gb.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 2015-2016 Google Inc.
27 return -ENODATA; in gb_audio_gb_get_topology()
31 return -ENOMEM; in gb_audio_gb_get_topology()
62 memcpy(value, &resp.value, sizeof(*value)); in gb_audio_gb_get_control()
76 memcpy(&req.value, value, sizeof(req.value)); in gb_audio_gb_set_control()
108 u32 *format, u32 *rate, u8 *channels, in gb_audio_gb_get_pcm() argument
124 *channels = resp.channels; in gb_audio_gb_get_pcm()
132 u32 format, u32 rate, u8 channels, in gb_audio_gb_set_pcm() argument
140 req.channels = channels; in gb_audio_gb_set_pcm()
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