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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Drenesas,cpg-mstp-clocks.yaml70 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
71 <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Drenesas,cpg-mstp-clocks.yaml70 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
71 <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
/kernel/linux/linux-5.10/drivers/phy/mediatek/
Dphy-mtk-ufs.c37 struct clk *mp_clk; member
84 phy->mp_clk = devm_clk_get(dev, "mp"); in ufs_mtk_phy_clk_init()
85 if (IS_ERR(phy->mp_clk)) { in ufs_mtk_phy_clk_init()
87 return PTR_ERR(phy->mp_clk); in ufs_mtk_phy_clk_init()
159 ret = clk_prepare_enable(phy->mp_clk); in ufs_mtk_phy_power_on()
161 dev_err(phy->dev, "mp_clk enable failed %d\n", ret); in ufs_mtk_phy_power_on()
182 clk_disable_unprepare(phy->mp_clk); in ufs_mtk_phy_power_off()
/kernel/linux/linux-6.6/arch/arm/boot/dts/renesas/
Dr8a73a4.dtsi591 mp_clk: mp@e6150080 { label
653 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
654 <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dr8a73a4.dtsi632 mp_clk: mp@e6150080 { label
694 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
695 <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
/kernel/linux/linux-6.6/drivers/clk/sunxi-ng/
Dccu-sun9i-a80.c558 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mp_clk, "mp", mp_parents, mp_table,
883 &mp_clk.common,
1029 [CLK_MP] = &mp_clk.common.hw,
Dccu-sun6i-a31.c547 static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", mp_parents,
925 &mp_clk.common,
1113 [CLK_MP] = &mp_clk.common.hw,
Dccu-sun8i-r40.c666 static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", de_parents,
933 &mp_clk.common,
1136 [CLK_MP] = &mp_clk.common.hw,
/kernel/linux/linux-5.10/drivers/clk/sunxi-ng/
Dccu-sun9i-a80.c558 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mp_clk, "mp", mp_parents, mp_table,
883 &mp_clk.common,
1029 [CLK_MP] = &mp_clk.common.hw,
Dccu-sun6i-a31.c546 static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", mp_parents,
924 &mp_clk.common,
1112 [CLK_MP] = &mp_clk.common.hw,
Dccu-sun8i-r40.c665 static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", de_parents,
932 &mp_clk.common,
1135 [CLK_MP] = &mp_clk.common.hw,