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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dal,alpine-msix.txt3 See arm,gic-v3.txt for SPI and MSI definitions.
7 - compatible: should be "al,alpine-msix"
8 - reg: physical base address and size of the registers
9 - interrupt-controller: identifies the node as an interrupt controller
10 - msi-controller: identifies the node as an PCI Message Signaled Interrupt
12 - al,msi-base-spi: SPI base of the MSI frame
13 - al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0
18 compatible = "al,alpine-msix";
20 interrupt-parent = <&gic>;
21 interrupt-controller;
[all …]
Dmarvell,odmi-controller.txt2 * Marvell ODMI for MSI support
4 Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller
5 which can be used by on-board peripheral for MSI interrupts.
9 - compatible : The value here should contain:
11 "marvell,ap806-odmi-controller", "marvell,odmi-controller".
13 - interrupt,controller : Identifies the node as an interrupt controller.
15 - msi-controller : Identifies the node as an MSI controller.
17 - marvell,odmi-frames : Number of ODMI frames available. Each frame
20 - reg : List of register definitions, one for each
23 - marvell,spi-base : List of GIC base SPI interrupts, one for each
[all …]
Darm,gic.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
14 interrupts (PPI), shared processor interrupts (SPI) and software
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
[all …]
Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
14 Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/
Dal,alpine-msix.txt3 See arm,gic-v3.txt for SPI and MSI definitions.
7 - compatible: should be "al,alpine-msix"
8 - reg: physical base address and size of the registers
9 - interrupt-controller: identifies the node as an interrupt controller
10 - msi-controller: identifies the node as an PCI Message Signaled Interrupt
12 - al,msi-base-spi: SPI base of the MSI frame
13 - al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0
18 compatible = "al,alpine-msix";
20 interrupt-parent = <&gic>;
21 interrupt-controller;
[all …]
Dmarvell,odmi-controller.txt2 * Marvell ODMI for MSI support
4 Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller
5 which can be used by on-board peripheral for MSI interrupts.
9 - compatible : The value here should contain:
11 "marvell,ap806-odmi-controller", "marvell,odmi-controller".
13 - interrupt,controller : Identifies the node as an interrupt controller.
15 - msi-controller : Identifies the node as an MSI controller.
17 - marvell,odmi-frames : Number of ODMI frames available. Each frame
20 - reg : List of register definitions, one for each
23 - marvell,spi-base : List of GIC base SPI interrupts, one for each
[all …]
Darm,gic.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
14 interrupts (PPI), shared processor interrupts (SPI) and software
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
[all …]
Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <maz@kernel.org>
14 Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/marvell/
Darmada-ap80x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
25 compatible = "arm,psci-0.2";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/marvell/
Darmada-ap80x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
25 compatible = "arm,psci-0.2";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/broadcom/northstar2/
Dns2.dtsi35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/clock/bcm-ns2.h>
40 interrupt-parent = <&gic>;
41 #address-cells = <2>;
42 #size-cells = <2>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a57";
52 enable-method = "psci";
53 next-level-cache = <&CLUSTER0_L2>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/broadcom/northstar2/
Dns2.dtsi35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/clock/bcm-ns2.h>
40 interrupt-parent = <&gic>;
41 #address-cells = <2>;
42 #size-cells = <2>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a57";
52 enable-method = "psci";
53 next-level-cache = <&CLUSTER0_L2>;
[all …]
/kernel/linux/linux-5.10/drivers/irqchip/
Dirq-gic-v2m.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ARM GIC v2m MSI(-X) support
16 #include <linux/dma-iommu.h>
21 #include <linux/msi.h>
26 #include <linux/irqchip/arm-gic.h>
31 * [25:16] lowest SPI assigned to MSI
33 * [9:0] Numer of SPIs assigned to MSI
49 /* APM X-Gene with GICv2m MSI_IIDR register value */
66 void __iomem *base; /* GICv2m virt address */ member
67 u32 spi_start; /* The SPI number that MSIs start */
[all …]
Dirq-mvebu-icu.c5 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
18 #include <linux/msi.h>
23 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
53 void __iomem *base; member
75 const struct mvebu_icu_subset_data *subset = msi_data->subset_data; in mvebu_icu_init()
77 if (atomic_cmpxchg(&msi_data->initialized, false, true)) in mvebu_icu_init()
80 /* Set 'SET' ICU SPI message address in AP */ in mvebu_icu_init()
81 writel_relaxed(msg[0].address_hi, icu->base + subset->offset_set_ah); in mvebu_icu_init()
82 writel_relaxed(msg[0].address_lo, icu->base + subset->offset_set_al); in mvebu_icu_init()
84 if (subset->icu_group != ICU_GRP_NSR) in mvebu_icu_init()
[all …]
Dirq-mvebu-odmi.c4 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 #define pr_fmt(fmt) "GIC-ODMI: " fmt
17 #include <linux/msi.h>
20 #include <dt-bindings/interrupt-controller/arm-gic.h>
35 #define NODMIS_MASK (NODMIS_PER_FRAME - 1)
39 void __iomem *base; member
56 if (WARN_ON(d->hwirq >= odmis_count * NODMIS_PER_FRAME)) in odmi_compose_msi_msg()
59 odmi = &odmis[d->hwirq >> NODMIS_SHIFT]; in odmi_compose_msi_msg()
60 odmin = d->hwirq & NODMIS_MASK; in odmi_compose_msi_msg()
62 addr = odmi->res.start + GICP_ODMIN_SET; in odmi_compose_msi_msg()
[all …]
Dirq-mvebu-sei.c1 // SPDX-License-Identifier: GPL-2.0
3 #define pr_fmt(fmt) "mvebu-sei: " fmt
11 #include <linux/msi.h>
41 void __iomem *base; member
48 /* Lock on MSI allocations/releases */
59 u32 reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_ack_irq()
61 writel_relaxed(BIT(SEI_IRQ_REG_BIT(d->hwirq)), in mvebu_sei_ack_irq()
62 sei->base + GICP_SECR(reg_idx)); in mvebu_sei_ack_irq()
68 u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_mask_irq()
72 raw_spin_lock_irqsave(&sei->mask_lock, flags); in mvebu_sei_mask_irq()
[all …]
Dirq-alpine-msi.c6 * Antoine Tenart <antoine.tenart@free-electrons.com>
16 #include <linux/irqchip/arm-gic.h>
17 #include <linux/msi.h>
26 #include <asm/msi.h>
63 spin_lock(&priv->msi_map_lock); in alpine_msix_allocate_sgi()
65 first = bitmap_find_next_zero_area(priv->msi_map, priv->num_spis, 0, in alpine_msix_allocate_sgi()
67 if (first >= priv->num_spis) { in alpine_msix_allocate_sgi()
68 spin_unlock(&priv->msi_map_lock); in alpine_msix_allocate_sgi()
69 return -ENOSPC; in alpine_msix_allocate_sgi()
72 bitmap_set(priv->msi_map, first, num_req); in alpine_msix_allocate_sgi()
[all …]
/kernel/linux/linux-6.6/drivers/irqchip/
Dirq-gic-v2m.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ARM GIC v2m MSI(-X) support
21 #include <linux/msi.h>
26 #include <linux/irqchip/arm-gic.h>
27 #include <linux/irqchip/arm-gic-common.h>
32 * [25:16] lowest SPI assigned to MSI
34 * [9:0] Numer of SPIs assigned to MSI
50 /* APM X-Gene with GICv2m MSI_IIDR register value */
67 void __iomem *base; /* GICv2m virt address */ member
68 u32 spi_start; /* The SPI number that MSIs start */
[all …]
Dirq-mvebu-icu.c5 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
18 #include <linux/msi.h>
23 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
53 void __iomem *base; member
75 const struct mvebu_icu_subset_data *subset = msi_data->subset_data; in mvebu_icu_init()
77 if (atomic_cmpxchg(&msi_data->initialized, false, true)) in mvebu_icu_init()
80 /* Set 'SET' ICU SPI message address in AP */ in mvebu_icu_init()
81 writel_relaxed(msg[0].address_hi, icu->base + subset->offset_set_ah); in mvebu_icu_init()
82 writel_relaxed(msg[0].address_lo, icu->base + subset->offset_set_al); in mvebu_icu_init()
84 if (subset->icu_group != ICU_GRP_NSR) in mvebu_icu_init()
[all …]
Dirq-mvebu-odmi.c4 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 #define pr_fmt(fmt) "GIC-ODMI: " fmt
17 #include <linux/msi.h>
20 #include <dt-bindings/interrupt-controller/arm-gic.h>
35 #define NODMIS_MASK (NODMIS_PER_FRAME - 1)
39 void __iomem *base; member
56 if (WARN_ON(d->hwirq >= odmis_count * NODMIS_PER_FRAME)) in odmi_compose_msi_msg()
59 odmi = &odmis[d->hwirq >> NODMIS_SHIFT]; in odmi_compose_msi_msg()
60 odmin = d->hwirq & NODMIS_MASK; in odmi_compose_msi_msg()
62 addr = odmi->res.start + GICP_ODMIN_SET; in odmi_compose_msi_msg()
[all …]
Dirq-mvebu-sei.c1 // SPDX-License-Identifier: GPL-2.0
3 #define pr_fmt(fmt) "mvebu-sei: " fmt
11 #include <linux/msi.h>
41 void __iomem *base; member
48 /* Lock on MSI allocations/releases */
59 u32 reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_ack_irq()
61 writel_relaxed(BIT(SEI_IRQ_REG_BIT(d->hwirq)), in mvebu_sei_ack_irq()
62 sei->base + GICP_SECR(reg_idx)); in mvebu_sei_ack_irq()
68 u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_mask_irq()
72 raw_spin_lock_irqsave(&sei->mask_lock, flags); in mvebu_sei_mask_irq()
[all …]
Dirq-alpine-msi.c6 * Antoine Tenart <antoine.tenart@free-electrons.com>
16 #include <linux/irqchip/arm-gic.h>
17 #include <linux/msi.h>
26 #include <asm/msi.h>
63 spin_lock(&priv->msi_map_lock); in alpine_msix_allocate_sgi()
65 first = bitmap_find_next_zero_area(priv->msi_map, priv->num_spis, 0, in alpine_msix_allocate_sgi()
67 if (first >= priv->num_spis) { in alpine_msix_allocate_sgi()
68 spin_unlock(&priv->msi_map_lock); in alpine_msix_allocate_sgi()
69 return -ENOSPC; in alpine_msix_allocate_sgi()
72 bitmap_set(priv->msi_map, first, num_req); in alpine_msix_allocate_sgi()
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/amd/
Damd-overdrive.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 /include/ "amd-seattle-soc.dtsi"
14 compatible = "amd,seattle-overdrive", "amd,seattle";
17 stdout-path = &serial0;
48 compatible = "mmc-spi-slot";
50 spi-max-frequency = <20000000>;
51 voltage-ranges = <3200 3400>;
53 interrupt-parent = <&gpio0>;
57 pl022,com-mode = <0x0>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dalpine.dtsi27 #include <dt-bindings/interrupt-controller/arm-gic.h>
30 #address-cells = <2>;
31 #size-cells = <2>;
42 #address-cells = <1>;
43 #size-cells = <0>;
44 enable-method = "al,alpine-smp";
47 compatible = "arm,cortex-a15";
50 clock-frequency = <1700000000>;
54 compatible = "arm,cortex-a15";
57 clock-frequency = <1700000000>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/amazon/
Dalpine.dtsi27 #include <dt-bindings/interrupt-controller/arm-gic.h>
30 #address-cells = <2>;
31 #size-cells = <2>;
42 #address-cells = <1>;
43 #size-cells = <0>;
44 enable-method = "al,alpine-smp";
47 compatible = "arm,cortex-a15";
50 clock-frequency = <1700000000>;
54 compatible = "arm,cortex-a15";
57 clock-frequency = <1700000000>;
[all …]

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