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/kernel/linux/linux-6.6/arch/arm64/boot/dts/mediatek/
Dmt8167.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt8167-clk.h>
9 #include <dt-bindings/memory/mt8167-larb-port.h>
10 #include <dt-bindings/power/mt8167-power.h>
12 #include "mt8167-pinfunc.h"
17 compatible = "mediatek,mt8167";
21 compatible = "mediatek,mt8167-topckgen", "syscon";
23 #clock-cells = <1>;
27 compatible = "mediatek,mt8167-infracfg", "syscon";
29 #clock-cells = <1>;
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/power/
Dmediatek,power-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek Power Domains Controller
10 - MandyJH Liu <mandyjh.liu@mediatek.com>
11 - Matthias Brugger <mbrugger@suse.com>
14 Mediatek processors include support for multiple power domains which can be
15 powered up/down by software based on different application scenes to save power.
17 IP cores belonging to a power domain should contain a 'power-domains'
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dmediatek,smi-larb.txt6 - compatible : must be one of :
7 "mediatek,mt2701-smi-larb"
8 "mediatek,mt2712-smi-larb"
9 "mediatek,mt6779-smi-larb"
10 "mediatek,mt7623-smi-larb", "mediatek,mt2701-smi-larb"
11 "mediatek,mt8167-smi-larb"
12 "mediatek,mt8173-smi-larb"
13 "mediatek,mt8183-smi-larb"
14 - reg : the register and size of this local arbiter.
15 - mediatek,smi : a phandle to the smi_common node.
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Dmediatek,smi-common.txt8 generation 2: mt2712, mt6779, mt8167, mt8173 and mt8183.
18 - compatible : must be one of :
19 "mediatek,mt2701-smi-common"
20 "mediatek,mt2712-smi-common"
21 "mediatek,mt6779-smi-common"
22 "mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
23 "mediatek,mt8167-smi-common"
24 "mediatek,mt8173-smi-common"
25 "mediatek,mt8183-smi-common"
26 - reg : the register and size of the SMI block.
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/
Dmediatek,smi-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Yong Wu <yong.wu@mediatek.com>
19 generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8186, mt8188, mt8192 and mt8195.
31 - enum:
32 - mediatek,mt2701-smi-common
33 - mediatek,mt2712-smi-common
34 - mediatek,mt6779-smi-common
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Dmediatek,smi-larb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-larb.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Yong Wu <yong.wu@mediatek.com>
19 - enum:
20 - mediatek,mt2701-smi-larb
21 - mediatek,mt2712-smi-larb
22 - mediatek,mt6779-smi-larb
23 - mediatek,mt6795-smi-larb
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/kernel/linux/linux-6.6/drivers/pmdomain/mediatek/
Dmt8167-pm-domains.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 #include "mtk-pm-domains.h"
7 #include <dt-bindings/power/mt8167-power.h>
13 * MT8167 power domain support
Dmtk-pm-domains.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
19 #include "mt6795-pm-domains.h"
20 #include "mt8167-pm-domains.h"
21 #include "mt8173-pm-domains.h"
22 #include "mt8183-pm-domains.h"
23 #include "mt8186-pm-domains.h"
24 #include "mt8188-pm-domains.h"
25 #include "mt8192-pm-domains.h"
26 #include "mt8195-pm-domains.h"
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/iommu/
Dmediatek,iommu.txt6 ARM Short-Descriptor translation table format for address translation.
14 +--------+
16 gals0-rx gals1-rx (Global Async Local Sync rx)
19 gals0-tx gals1-tx (Global Async Local Sync tx)
21 +--------+
25 +----------------+-------
27 | gals-rx There may be GALS in some larbs.
30 | gals-tx
36 +-----+-----+ +----+----+
46 directly with EMI. And also SMI help control the power domain and clocks for
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/iommu/
Dmediatek,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yong Wu <yong.wu@mediatek.com>
16 ARM Short-Descriptor translation table format for address translation.
24 +--------+
26 gals0-rx gals1-rx (Global Async Local Sync rx)
29 gals0-tx gals1-tx (Global Async Local Sync tx)
31 +--------+
35 +----------------+-------
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mfd/
Dmediatek,mt8195-scpsys.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/mediatek,mt8195-scpsys.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - MandyJH Liu <mandyjh.liu@mediatek.com>
14 power management tasks. The tasks include MTCMOS power
20 - enum:
21 - mediatek,mt8167-scpsys
22 - mediatek,mt8173-scpsys
23 - mediatek,mt8183-scpsys
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/mediatek/
Dmediatek,topckgen.txt8 - compatible: Should be one of:
9 - "mediatek,mt2701-topckgen"
10 - "mediatek,mt2712-topckgen", "syscon"
11 - "mediatek,mt6765-topckgen", "syscon"
12 - "mediatek,mt6779-topckgen", "syscon"
13 - "mediatek,mt6797-topckgen"
14 - "mediatek,mt7622-topckgen"
15 - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
16 - "mediatek,mt7629-topckgen"
17 - "mediatek,mt8135-topckgen"
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Dmediatek,infracfg.txt9 - compatible: Should be one of:
10 - "mediatek,mt2701-infracfg", "syscon"
11 - "mediatek,mt2712-infracfg", "syscon"
12 - "mediatek,mt6765-infracfg", "syscon"
13 - "mediatek,mt6779-infracfg_ao", "syscon"
14 - "mediatek,mt6797-infracfg", "syscon"
15 - "mediatek,mt7622-infracfg", "syscon"
16 - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
17 - "mediatek,mt7629-infracfg", "syscon"
18 - "mediatek,mt8135-infracfg", "syscon"
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,color.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
25 - enum:
26 - mediatek,mt2701-disp-color
27 - mediatek,mt8167-disp-color
28 - mediatek,mt8173-disp-color
29 - items:
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Dmediatek,dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
12 - Jitao Shi <jitao.shi@mediatek.com>
13 - Xinlei Lee <xinlei.lee@mediatek.com>
17 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
21 - $ref: /schemas/display/dsi-controller.yaml#
26 - enum:
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/mediatek/
Dmediatek,mmsys.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matthias Brugger <matthias.bgg@gmail.com>
18 pattern: "^syscon@[0-9a-f]+$"
22 - items:
23 - enum:
24 - mediatek,mt2701-mmsys
25 - mediatek,mt2712-mmsys
26 - mediatek,mt6765-mmsys
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/mediatek/
Dmediatek,mutex.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
15 Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
27 - mediatek,mt2701-disp-mutex
28 - mediatek,mt2712-disp-mutex
29 - mediatek,mt6795-disp-mutex
30 - mediatek,mt8167-disp-mutex
[all …]
/kernel/linux/linux-5.10/drivers/memory/
Dmtk-smi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2016 MediaTek Inc.
17 #include <dt-bindings/memory/mt2701-larb-port.h>
22 /* mt8167 */
36 * or non-security.
96 ret = clk_prepare_enable(smi->clk_apb); in mtk_smi_clk_enable()
100 ret = clk_prepare_enable(smi->clk_smi); in mtk_smi_clk_enable()
104 ret = clk_prepare_enable(smi->clk_gals0); in mtk_smi_clk_enable()
108 ret = clk_prepare_enable(smi->clk_gals1); in mtk_smi_clk_enable()
115 clk_disable_unprepare(smi->clk_gals0); in mtk_smi_clk_enable()
[all …]
/kernel/linux/linux-6.6/drivers/cpufreq/
Dmediatek-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
30 * on each CPU power/clock domain of Mediatek SoCs. Each CPU cluster in
33 * 100mV < Vsram - Vproc < 200mV
71 if (cpumask_test_cpu(cpu, &info->cpus)) in mtk_cpu_dvfs_info_lookup()
81 const struct mtk_cpufreq_platform_data *soc_data = info->soc_data; in mtk_cpufreq_voltage_tracking()
82 struct regulator *proc_reg = info->proc_reg; in mtk_cpufreq_voltage_tracking()
83 struct regulator *sram_reg = info->sram_reg; in mtk_cpufreq_voltage_tracking()
85 int retry = info->vtrack_max; in mtk_cpufreq_voltage_tracking()
89 dev_err(info->cpu_dev, in mtk_cpufreq_voltage_tracking()
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/kernel/linux/linux-6.6/drivers/iommu/
Dmtk_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2016 MediaTek Inc.
6 #include <linux/arm-smccc.h>
17 #include <linux/io-pgtable.h>
35 #include <dt-bindings/memory/mtk-memory-port.h>
151 ((((pdata)->flags) & (mask)) == (_x))
207 * is in 4G-8G and cam is in 8G-12G. Meanwhile, some masters may have the
209 * 0x40000000-0x44000000.
271 * In the sharing pgtable case, list data->list to the global list like m4ulist.
272 * In the non-sharing pgtable case, list data->list to the itself hw_list_head.
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