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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/mediatek/
Dmediatek,apmixedsys.txt1 Mediatek apmixedsys controller
4 The Mediatek apmixedsys controller provides the PLLs to the system.
8 - compatible: Should be one of:
9 - "mediatek,mt2701-apmixedsys"
10 - "mediatek,mt2712-apmixedsys", "syscon"
11 - "mediatek,mt6765-apmixedsys", "syscon"
12 - "mediatek,mt6779-apmixedsys", "syscon"
13 - "mediatek,mt6797-apmixedsys"
14 - "mediatek,mt7622-apmixedsys"
15 - "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dmediatek,apmixedsys.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,apmixedsys.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Turquette <mturquette@baylibre.com>
11 - Stephen Boyd <sboyd@kernel.org>
14 The Mediatek apmixedsys controller provides PLLs to the system.
15 The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
20 - enum:
21 - mediatek,mt6797-apmixedsys
[all …]
Dmediatek,mt8186-fhctl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8186-fhctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Edward-JW Yang <edward-jw.yang@mediatek.com>
20 - mediatek,mt6795-fhctl
21 - mediatek,mt8173-fhctl
22 - mediatek,mt8186-fhctl
23 - mediatek,mt8192-fhctl
24 - mediatek,mt8195-fhctl
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/thermal/
Dmediatek-thermal.txt4 which measures the on-SoC temperatures. This device does not have its own ADC,
7 apmixedsys register space via AHB bus accesses, so a phandle to the APMIXEDSYS
11 - compatible:
12 - "mediatek,mt8173-thermal" : For MT8173 family of SoCs
13 - "mediatek,mt2701-thermal" : For MT2701 family of SoCs
14 - "mediatek,mt2712-thermal" : For MT2712 family of SoCs
15 - "mediatek,mt7622-thermal" : For MT7622 SoC
16 - "mediatek,mt8183-thermal" : For MT8183 family of SoCs
17 - reg: Address range of the thermal controller
18 - interrupts: IRQ for the thermal controller
[all …]
/kernel/linux/linux-6.6/drivers/clk/mediatek/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o rese…
3 obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o
5 obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o
6 obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o
7 obj-$(CONFIG_COMMON_CLK_MT6765_CAMSYS) += clk-mt6765-cam.o
8 obj-$(CONFIG_COMMON_CLK_MT6765_IMGSYS) += clk-mt6765-img.o
9 obj-$(CONFIG_COMMON_CLK_MT6765_MIPI0ASYS) += clk-mt6765-mipi0a.o
10 obj-$(CONFIG_COMMON_CLK_MT6765_MMSYS) += clk-mt6765-mm.o
11 obj-$(CONFIG_COMMON_CLK_MT6765_VCODECSYS) += clk-mt6765-vcodec.o
[all …]
Dclk-mt8173-apmixedsys.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/clock/mt8173-clk.h>
12 #include "clk-fhctl.h"
13 #include "clk-mtk.h"
14 #include "clk-pll.h"
15 #include "clk-pllfh.h"
135 { .compatible = "mediatek,mt8173-apmixedsys" },
142 const u8 *fhctl_node = "mediatek,mt8173-fhctl"; in clk_mt8173_apmixed_probe()
143 struct device_node *node = pdev->dev.of_node; in clk_mt8173_apmixed_probe()
151 return -ENOMEM; in clk_mt8173_apmixed_probe()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/thermal/
Dmediatek-thermal.txt4 which measures the on-SoC temperatures. This device does not have its own ADC,
7 apmixedsys register space via AHB bus accesses, so a phandle to the APMIXEDSYS
11 - compatible:
12 - "mediatek,mt8173-thermal" : For MT8173 family of SoCs
13 - "mediatek,mt2701-thermal" : For MT2701 family of SoCs
14 - "mediatek,mt2712-thermal" : For MT2712 family of SoCs
15 - "mediatek,mt7622-thermal" : For MT7622 SoC
16 - "mediatek,mt7981-thermal", "mediatek,mt7986-thermal" : For MT7981 SoC
17 - "mediatek,mt7986-thermal" : For MT7986 SoC
18 - "mediatek,mt8183-thermal" : For MT8183 family of SoCs
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/mediatek/
Dmt8173.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/mt8173-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/memory/mt8173-larb-port.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/power/mt8173-power.h>
13 #include <dt-bindings/reset/mt8173-resets.h>
14 #include <dt-bindings/gce/mt8173-gce.h>
15 #include <dt-bindings/thermal/thermal.h>
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/mediatek/
Dmt8173.dtsi14 #include <dt-bindings/clock/mt8173-clk.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/memory/mt8173-larb-port.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/power/mt8173-power.h>
20 #include <dt-bindings/reset/mt8173-resets.h>
21 #include <dt-bindings/gce/mt8173-gce.h>
22 #include <dt-bindings/thermal/thermal.h>
23 #include "mt8173-pinfunc.h"
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/
Dmediatek,vcodec-decoder.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/mediatek,vcodec-decoder.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Yunfei Dong <yunfei.dong@mediatek.com>
20 - mediatek,mt8173-vcodec-dec
21 - mediatek,mt8183-vcodec-dec
27 reg-names:
29 - const: misc
30 - const: ld
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/
Dmediatek-vcodec.txt7 - compatible : "mediatek,mt8173-vcodec-enc" for MT8173 encoder
8 "mediatek,mt8183-vcodec-enc" for MT8183 encoder.
9 "mediatek,mt8173-vcodec-dec" for MT8173 decoder.
10 - reg : Physical base address of the video codec registers and length of
12 - interrupts : interrupt number to the cpu.
13 - mediatek,larb : must contain the local arbiters in the current Socs.
14 - clocks : list of clock specifiers, corresponding to entries in
15 the clock-names property.
16 - clock-names: encoder must contain "venc_sel_src", "venc_sel",,
20 - iommus : should point to the respective IOMMU block with master port as
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dphy-mtk-tphy.txt1 MediaTek T-PHY binding
2 --------------------------
4 T-phy controller supports physical layer functionality for a number of
8 - compatible : should be one of
9 "mediatek,generic-tphy-v1"
10 "mediatek,generic-tphy-v2"
11 "mediatek,mt2701-u3phy" (deprecated)
12 "mediatek,mt2712-u3phy" (deprecated)
13 "mediatek,mt8173-u3phy";
14 make use of "mediatek,generic-tphy-v1" on mt2701 instead and
[all …]
/kernel/linux/linux-5.10/drivers/thermal/
Dmtk_thermal.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/nvmem-consumer.h>
91 /* MT8173 thermal sensors */
101 /* The total number of temperature sensors in the MT8173 */
104 /* The number of banks in the MT8173 */
110 /* The number of controller in the MT8173 */
118 * These macros could be used for MT8183, MT8173, MT2701, and MT2712.
120 * MT8173 has 5 sensors and needs 5 VTS calibration data.
316 /* MT8173 thermal sensor data */
388 * The MT8173 thermal controller has four banks. Each bank can read up to
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,dpi.txt5 provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
9 - compatible: "mediatek,<chip>-dpi"
10 the supported chips are mt2701, mt7623, mt8173 and mt8183.
11 - reg: Physical base address and length of the controller's registers
12 - interrupts: The interrupt signal from the function block.
13 - clocks: device clocks
14 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
15 - clock-names: must contain "pixel", "engine", and "pll"
16 - port: Output port node with endpoint definitions as described in
21 - pinctrl-names: Contain "default" and "sleep".
[all …]
Dmediatek,hdmi.txt8 - compatible: Should be "mediatek,<chip>-hdmi".
9 - the supported chips are mt2701, mt7623 and mt8173
10 - reg: Physical base address and length of the controller's registers
11 - interrupts: The interrupt signal from the function block.
12 - clocks: device clocks
13 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
14 - clock-names: must contain "pixel", "pll", "bclk", and "spdif".
15 - phys: phandle link to the HDMI PHY node.
16 See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
17 - phy-names: must contain "hdmi"
[all …]
/kernel/linux/linux-6.6/drivers/thermal/mediatek/
Dauxadc_thermal.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/nvmem-consumer.h>
93 /* MT8173 thermal sensors */
103 /* The total number of temperature sensors in the MT8173 */
106 /* The number of banks in the MT8173 */
112 /* The number of controller in the MT8173 */
119 #define MT8173_TEMP_MIN -20000
124 * These macros could be used for MT8183, MT8173, MT2701, and MT2712.
126 * MT8173 has 5 sensors and needs 5 VTS calibration data.
374 /* MT8173 thermal sensor data */
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dmediatek,hdmi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12 - Philipp Zabel <p.zabel@pengutronix.de>
13 - Chunfeng Yun <chunfeng.yun@mediatek.com>
16 The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
21 pattern: "^hdmi-phy@[0-9a-f]+$"
25 - items:
[all …]
Dmediatek,tphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek T-PHY Controller
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The T-PHY controller supports physical layer functionality for a number of
17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
19 -----------------------------------
67 pattern: "^t-phy(@[0-9a-f]+)?$"
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,dpi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - CK Hu <ck.hu@mediatek.com>
11 - Jitao shi <jitao.shi@mediatek.com>
15 subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a
21 - enum:
22 - mediatek,mt2701-dpi
23 - mediatek,mt7623-dpi
24 - mediatek,mt8173-dpi
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/cpufreq/
Dcpufreq-mediatek.txt5 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
6 - clock-names: Should contain the following:
7 "cpu" - The multiplexer for clock input of CPU cluster.
8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
11 Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
13 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
15 - proc-supply: Regulator for Vproc of CPU cluster.
18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
23 - mediatek,cci:
30 - #cooling-cells:
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/cpufreq/
Dcpufreq-mediatek.txt5 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
6 - clock-names: Should contain the following:
7 "cpu" - The multiplexer for clock input of CPU cluster.
8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
11 Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
13 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp.txt
15 - proc-supply: Regulator for Vproc of CPU cluster.
18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
23 - #cooling-cells:
25 Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dmt7623.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017-2018 MediaTek Inc.
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/clock/mt2701-clk.h>
13 #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
14 #include <dt-bindings/power/mt2701-power.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/phy/phy.h>
17 #include <dt-bindings/reset/mt2701-resets.h>
[all …]
Dmt7623n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright © 2017-2020 MediaTek Inc.
10 #include <dt-bindings/memory/mt2701-larb-port.h>
19 compatible = "mediatek,mt7623-g3dsys",
20 "mediatek,mt2701-g3dsys",
23 #clock-cells = <1>;
24 #reset-cells = <1>;
28 compatible = "mediatek,mt7623-mali", "arm,mali-450";
41 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
46 clock-names = "bus", "core";
[all …]
Dmt2701.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt2701-clk.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/mt2701-power.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/memory/mt2701-larb-port.h>
14 #include <dt-bindings/reset/mt2701-resets.h>
15 #include "mt2701-pinfunc.h"
18 #address-cells = <2>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/mediatek/
Dmt7623n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright © 2017-2020 MediaTek Inc.
10 #include <dt-bindings/memory/mt2701-larb-port.h>
19 compatible = "mediatek,mt7623-g3dsys",
20 "mediatek,mt2701-g3dsys",
23 #clock-cells = <1>;
24 #reset-cells = <1>;
28 compatible = "mediatek,mt7623-mali", "arm,mali-450";
41 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
46 clock-names = "bus", "core";
[all …]

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