| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/mediatek/ |
| D | mediatek,dsi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek DSI Controller
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
12 - Jitao Shi <jitao.shi@mediatek.com>
13 - Xinlei Lee <xinlei.lee@mediatek.com>
16 The MediaTek DSI function block is a sink of the display subsystem and can
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| D | mediatek,rdma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
15 data into DMA. It provides real time data to the back-end panel
16 driver, such as DSI, DPI and DP_INTF.
26 - enum:
27 - mediatek,mt2701-disp-rdma
28 - mediatek,mt8173-disp-rdma
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/mediatek/ |
| D | mediatek,dsi.txt | 1 Mediatek DSI Device
4 The Mediatek DSI function block is a sink of the display subsystem and can
5 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
9 - compatible: "mediatek,<chip>-dsi"
10 - the supported chips are mt2701, mt7623, mt8173 and mt8183.
11 - reg: Physical base address and length of the controller's registers
12 - interrupts: The interrupt signal from the function block.
13 - clocks: device clocks
14 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
15 - clock-names: must contain "engine", "digital", and "hs"
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| D | mediatek,disp.txt | 25 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and
29 - compatible: "mediatek,<chip>-disp-<function>", one of
30 "mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc)
31 "mediatek,<chip>-disp-ovl-2l" - overlay (2 layers, blending, csc)
32 "mediatek,<chip>-disp-rdma" - read DMA / line buffer
33 "mediatek,<chip>-disp-wdma" - write DMA
34 "mediatek,<chip>-disp-ccorr" - color correction
35 "mediatek,<chip>-disp-color" - color processor
36 "mediatek,<chip>-disp-dither" - dither
37 "mediatek,<chip>-disp-aal" - adaptive ambient light controller
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | mediatek,dsi-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek MIPI Display Serial Interface (DSI) PHY
11 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12 - Philipp Zabel <p.zabel@pengutronix.de>
13 - Chunfeng Yun <chunfeng.yun@mediatek.com>
15 description: The MIPI DSI PHY supports up to 4-lane output.
19 pattern: "^dsi-phy@[0-9a-f]+$"
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| /kernel/linux/linux-6.6/drivers/phy/mediatek/ |
| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
6 obj-$(CONFIG_PHY_MTK_DP) += phy-mtk-dp.o
7 obj-$(CONFIG_PHY_MTK_PCIE) += phy-mtk-pcie.o
8 obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
9 obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
10 obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
12 phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o
13 phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
14 phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt8173.o
15 phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt8195.o
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| D | phy-mtk-mipi-dsi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "phy-mtk-mipi-dsi.h"
18 dev_dbg(mipi_tx->dev, "set rate: %lu Hz\n", rate); in mtk_mipi_tx_pll_set_rate()
20 mipi_tx->data_rate = rate; in mtk_mipi_tx_pll_set_rate()
30 return mipi_tx->data_rate; in mtk_mipi_tx_pll_recalc_rate()
39 ret = clk_prepare_enable(mipi_tx->pll_hw.clk); in mtk_mipi_tx_power_on()
43 /* Enable DSI Lane LDO outputs, disable pad tie low */ in mtk_mipi_tx_power_on()
44 mipi_tx->driver_data->mipi_tx_enable_signal(phy); in mtk_mipi_tx_power_on()
52 /* Enable pad tie low, disable DSI Lane LDO outputs */ in mtk_mipi_tx_power_off()
53 mipi_tx->driver_data->mipi_tx_disable_signal(phy); in mtk_mipi_tx_power_off()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/mediatek/ |
| D | mtk_drm_drv.c | 1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/dma-mapping.h>
50 if (info->num_planes != 1) in mtk_drm_mode_fb_create()
51 return ERR_PTR(-EINVAL); in mtk_drm_mode_fb_create()
316 { .compatible = "mediatek,mt2701-mmsys",
318 { .compatible = "mediatek,mt7623-mmsys",
320 { .compatible = "mediatek,mt2712-mmsys",
322 { .compatible = "mediatek,mt8167-mmsys",
324 { .compatible = "mediatek,mt8173-mmsys",
326 { .compatible = "mediatek,mt8183-mmsys",
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| D | mtk_dsi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
223 static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data) in mtk_dsi_mask() argument
225 u32 temp = readl(dsi->regs + offset); in mtk_dsi_mask()
227 writel((temp & ~mask) | (data & mask), dsi->regs + offset); in mtk_dsi_mask()
230 static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi) in mtk_dsi_phy_timconfig() argument
233 u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, 1000000); in mtk_dsi_phy_timconfig()
234 struct mtk_phy_timing *timing = &dsi->phy_timing; in mtk_dsi_phy_timconfig()
236 timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1; in mtk_dsi_phy_timconfig()
237 timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000; in mtk_dsi_phy_timconfig()
238 timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 - in mtk_dsi_phy_timconfig()
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| D | mtk_disp_rdma.c | 1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/soc/mediatek/mtk-cmdq.h>
52 #define RDMA_FIFO_SIZE(rdma) ((rdma)->data->fifo_size)
78 * struct mtk_disp_rdma - DISP_RDMA driver structure
96 writel(0x0, priv->regs + DISP_REG_RDMA_INT_STATUS); in mtk_disp_rdma_irq_handler()
98 if (!priv->vblank_cb) in mtk_disp_rdma_irq_handler()
101 priv->vblank_cb(priv->vblank_cb_data); in mtk_disp_rdma_irq_handler()
110 unsigned int tmp = readl(rdma->regs + reg); in rdma_update_bits()
113 writel(tmp, rdma->regs + reg); in rdma_update_bits()
122 rdma->vblank_cb = vblank_cb; in mtk_rdma_register_vblank_cb()
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/mediatek/ |
| D | mt8183.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt8183-clk.h>
9 #include <dt-bindings/gce/mt8183-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8183-larb-port.h>
13 #include <dt-bindings/power/mt8183-power.h>
14 #include <dt-bindings/reset/mt8183-resets.h>
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/thermal/thermal.h>
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| D | mt8192.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8192-clk.h>
9 #include <dt-bindings/gce/mt8192-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8192-larb-port.h>
13 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/power/mt8192-power.h>
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| D | mt8186.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
6 /dts-v1/;
7 #include <dt-bindings/clock/mt8186-clk.h>
8 #include <dt-bindings/gce/mt8186-gce.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/memory/mt8186-memory-port.h>
12 #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
13 #include <dt-bindings/power/mt8186-power.h>
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| /kernel/linux/linux-5.10/drivers/gpu/drm/mediatek/ |
| D | mtk_mipi_tx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
16 u32 temp = readl(mipi_tx->regs + offset); in mtk_mipi_tx_clear_bits()
18 writel(temp & ~bits, mipi_tx->regs + offset); in mtk_mipi_tx_clear_bits()
24 u32 temp = readl(mipi_tx->regs + offset); in mtk_mipi_tx_set_bits()
26 writel(temp | bits, mipi_tx->regs + offset); in mtk_mipi_tx_set_bits()
32 u32 temp = readl(mipi_tx->regs + offset); in mtk_mipi_tx_update_bits()
34 writel((temp & ~mask) | (data & mask), mipi_tx->regs + offset); in mtk_mipi_tx_update_bits()
42 dev_dbg(mipi_tx->dev, "set rate: %lu Hz\n", rate); in mtk_mipi_tx_pll_set_rate()
44 mipi_tx->data_rate = rate; in mtk_mipi_tx_pll_set_rate()
54 return mipi_tx->data_rate; in mtk_mipi_tx_pll_recalc_rate()
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| D | mtk_dsi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
221 static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data) in mtk_dsi_mask() argument
223 u32 temp = readl(dsi->regs + offset); in mtk_dsi_mask()
225 writel((temp & ~mask) | (data & mask), dsi->regs + offset); in mtk_dsi_mask()
228 static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi) in mtk_dsi_phy_timconfig() argument
231 u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, 1000000); in mtk_dsi_phy_timconfig()
232 struct mtk_phy_timing *timing = &dsi->phy_timing; in mtk_dsi_phy_timconfig()
234 timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1; in mtk_dsi_phy_timconfig()
235 timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000; in mtk_dsi_phy_timconfig()
236 timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 - in mtk_dsi_phy_timconfig()
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| /kernel/linux/linux-6.6/ |
| D | MAINTAINERS | 5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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