| /kernel/linux/linux-6.6/arch/arm/common/ |
| D | mcpm_head.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/common/mcpm_head.S -- kernel entry point for multi-cluster PM
6 * Copyright: (C) 2012-2013 Linaro Limited
8 * Refer to Documentation/arch/arm/cluster-pm-race-avoidance.rst
18 .arch armv7-a
28 1903: .asciz " cluster"
56 ubfx r10, r0, #8, #8 @ r10 = cluster
88 mla r8, r0, r10, r8 @ r8 = sync cluster base
96 @ At this point, the cluster cannot unexpectedly enter the GOING_DOWN
100 mla r11, r0, r10, r11 @ r11 = cluster first man lock
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| D | mcpm_entry.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/common/mcpm_entry.c -- entry point for multi-cluster PM
6 * Copyright: (C) 2012-2013 Linaro Limited
24 * see Documentation/arch/arm/cluster-pm-race-avoidance.rst.
34 static void __mcpm_cpu_going_down(unsigned int cpu, unsigned int cluster) in __mcpm_cpu_going_down() argument
36 mcpm_sync.clusters[cluster].cpus[cpu].cpu = CPU_GOING_DOWN; in __mcpm_cpu_going_down()
37 sync_cache_w(&mcpm_sync.clusters[cluster].cpus[cpu].cpu); in __mcpm_cpu_going_down()
42 * cluster can be torn down without disrupting this CPU.
47 static void __mcpm_cpu_down(unsigned int cpu, unsigned int cluster) in __mcpm_cpu_down() argument
50 mcpm_sync.clusters[cluster].cpus[cpu].cpu = CPU_DOWN; in __mcpm_cpu_down()
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| /kernel/linux/linux-5.10/arch/arm/common/ |
| D | mcpm_head.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/common/mcpm_head.S -- kernel entry point for multi-cluster PM
6 * Copyright: (C) 2012-2013 Linaro Limited
8 * Refer to Documentation/arm/cluster-pm-race-avoidance.rst
26 1903: .asciz " cluster"
54 ubfx r10, r0, #8, #8 @ r10 = cluster
86 mla r8, r0, r10, r8 @ r8 = sync cluster base
94 @ At this point, the cluster cannot unexpectedly enter the GOING_DOWN
98 mla r11, r0, r10, r11 @ r11 = cluster first man lock
104 bne mcpm_setup_wait @ wait for cluster setup if so
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| D | mcpm_entry.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/common/mcpm_entry.c -- entry point for multi-cluster PM
6 * Copyright: (C) 2012-2013 Linaro Limited
24 * see Documentation/arm/cluster-pm-race-avoidance.rst.
34 static void __mcpm_cpu_going_down(unsigned int cpu, unsigned int cluster) in __mcpm_cpu_going_down() argument
36 mcpm_sync.clusters[cluster].cpus[cpu].cpu = CPU_GOING_DOWN; in __mcpm_cpu_going_down()
37 sync_cache_w(&mcpm_sync.clusters[cluster].cpus[cpu].cpu); in __mcpm_cpu_going_down()
42 * cluster can be torn down without disrupting this CPU.
47 static void __mcpm_cpu_down(unsigned int cpu, unsigned int cluster) in __mcpm_cpu_down() argument
50 mcpm_sync.clusters[cluster].cpus[cpu].cpu = CPU_DOWN; in __mcpm_cpu_down()
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/cpu/ |
| D | cpu-topology.txt | 6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
39 2 - cpu-map node
42 The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct
46 - cpu-map node
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/cpu/ |
| D | cpu-topology.txt | 6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
39 2 - cpu-map node
42 The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct
46 - cpu-map node
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| /kernel/linux/linux-5.10/arch/arm/mach-sunxi/ |
| D | mc_smp.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
7 * arch/arm/mach-sunxi/mc_smp.c
9 * Based on Allwinner code, arch/arm/mach-exynos/mcpm-exynos.c, and
10 * arch/arm/mach-hisi/platmcpm.c
11 * Cluster cache enable trampoline code adapted from MCPM framework
14 #include <linux/arm-cci.h>
19 #include <linux/irqchip/arm-gic.h>
71 /* R_CPUCFG registers, specific to sun8i-a83t */
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| /kernel/linux/linux-6.6/arch/arm/mach-sunxi/ |
| D | mc_smp.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
7 * arch/arm/mach-sunxi/mc_smp.c
9 * Based on Allwinner code, arch/arm/mach-exynos/mcpm-exynos.c, and
10 * arch/arm/mach-hisi/platmcpm.c
11 * Cluster cache enable trampoline code adapted from MCPM framework
14 #include <linux/arm-cci.h>
19 #include <linux/irqchip/arm-gic.h>
70 /* R_CPUCFG registers, specific to sun8i-a83t */
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| /kernel/linux/linux-5.10/Documentation/arm/ |
| D | cluster-pm-race-avoidance.rst | 2 Cluster-wide Power-up/power-down race avoidance algorithm
6 cluster setup and teardown operations and to manage hardware coherency
16 ---------
29 cluster-level operations are only performed when it is truly safe to do
34 are not immediately enabled when a cluster powers up. Since enabling or
35 disabling those mechanisms may itself be a non-atomic operation (such as
38 power-down and power-up at the cluster level.
46 -----------
48 Each cluster and CPU is assigned a state, as follows:
50 - DOWN
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| /kernel/linux/linux-6.6/Documentation/arch/arm/ |
| D | cluster-pm-race-avoidance.rst | 2 Cluster-wide Power-up/power-down race avoidance algorithm
6 cluster setup and teardown operations and to manage hardware coherency
16 ---------
29 cluster-level operations are only performed when it is truly safe to do
34 are not immediately enabled when a cluster powers up. Since enabling or
35 disabling those mechanisms may itself be a non-atomic operation (such as
38 power-down and power-up at the cluster level.
46 -----------
48 Each cluster and CPU is assigned a state, as follows:
50 - DOWN
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| /kernel/linux/linux-6.6/arch/arm/mach-versatile/ |
| D | spc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
28 #define SPCLOG "vexpress-spc: "
39 /* SPC wake-up IRQs status and mask */
46 /* SPC per-CPU mailboxes */
50 /* SPC CPU/cluster reset statue */
68 /* wake-up interrupt masks */
71 /* TC2 static dual-cluster configuration */
75 * Even though the SPC takes max 3-5 ms to complete any OPP/COMMS
97 * A15s cluster identifier
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| D | platsmp-vexpress.c | 1 // SPDX-License-Identifier: GPL-2.0-only
27 * The best way to detect a multi-cluster configuration in vexpress_smp_init_ops()
40 cci_node = of_parse_phandle(cpu_node, "cci-control-port", 0); in vexpress_smp_init_ops()
57 { .compatible = "arm,cortex-a5-scu", },
58 { .compatible = "arm,cortex-a9-scu", },
72 * system-wide flags register. The boot monitor waits in vexpress_smp_dt_prepare_cpus()
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| /kernel/linux/linux-5.10/arch/arm/mach-vexpress/ |
| D | spc.c | 20 #include <linux/clk-provider.h>
36 #define SPCLOG "vexpress-spc: "
47 /* SPC wake-up IRQs status and mask */
54 /* SPC per-CPU mailboxes */
58 /* SPC CPU/cluster reset statue */
76 /* wake-up interrupt masks */
79 /* TC2 static dual-cluster configuration */
83 * Even though the SPC takes max 3-5 ms to complete any OPP/COMMS
105 * A15s cluster identifier
119 static inline bool cluster_is_a15(u32 cluster) in cluster_is_a15() argument
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| D | platsmp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-vexpress/platsmp.c
30 * The best way to detect a multi-cluster configuration in vexpress_smp_init_ops()
43 cci_node = of_parse_phandle(cpu_node, "cci-control-port", 0); in vexpress_smp_init_ops()
60 { .compatible = "arm,cortex-a5-scu", },
61 { .compatible = "arm,cortex-a9-scu", },
75 * system-wide flags register. The boot monitor waits in vexpress_smp_dt_prepare_cpus()
|
| /kernel/linux/linux-6.6/Documentation/admin-guide/perf/ |
| D | hisi-pmu.rst | 10 The HiSilicon SoC encapsulates multiple CPU and IO dies. Each CPU cluster
12 called Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has
13 two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.
16 -------------------------------
28 name will appear in event listing as hisi_sccl<sccl-id>_module<index-id>.
29 where "sccl-id" is the identifier of the SCCL and "index-id" is the index of
45 ------------------------------------------
47 ------------------------------------------
49 ------------------------------------------
51 ------------------------------------------
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| /kernel/linux/linux-6.6/drivers/gpu/drm/rockchip/ |
| D | rockchip_vop2_reg.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Andy Yan <andy.yan@rock-chips.com>
126 * rk3568 vop with 2 cluster, 2 esmart win, 2 smart win.
127 * Every cluster can work as 4K win or split into two win.
128 * All win in cluster support AFBCD.
130 * Every esmart win and smart win support 4 Multi-region.
134 * * Cluster: bicubic for horizontal scale up, others use bilinear
136 * * nearest-neighbor/bilinear/bicubic for scale up
137 * * nearest-neighbor/bilinear/average for scale down
140 * @TODO describe the wind like cpu-map dt nodes;
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| /kernel/linux/linux-5.10/drivers/perf/ |
| D | qcom_l2_pmu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2017 The Linux Foundation. All rights reserved.
26 #include <soc/qcom/kryo-l2-accessors.h>
121 * The cache is made up of one or more clusters, each cluster has its own PMU.
122 * Each cluster is associated with one or more CPUs.
125 * Events can be envisioned as a 2-dimensional array. Each column represents
143 /* The CPU that is used for collecting events on this cluster */
145 /* All the CPUs associated with this cluster */
166 return *per_cpu_ptr(l2cache_pmu->pmu_cluster, cpu); in get_cluster_pmu()
243 static void cluster_pmu_set_resr(struct cluster_pmu *cluster, in cluster_pmu_set_resr() argument
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| /kernel/linux/linux-6.6/drivers/perf/ |
| D | qcom_l2_pmu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2017 The Linux Foundation. All rights reserved.
26 #include <soc/qcom/kryo-l2-accessors.h>
121 * The cache is made up of one or more clusters, each cluster has its own PMU.
122 * Each cluster is associated with one or more CPUs.
125 * Events can be envisioned as a 2-dimensional array. Each column represents
143 /* The CPU that is used for collecting events on this cluster */
145 /* All the CPUs associated with this cluster */
166 return *per_cpu_ptr(l2cache_pmu->pmu_cluster, cpu); in get_cluster_pmu()
243 static void cluster_pmu_set_resr(struct cluster_pmu *cluster, in cluster_pmu_set_resr() argument
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/ |
| D | arm,cci-400.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 ARM multi-cluster systems maintain intra-cluster coherency through a cache
24 pattern: "^cci(@[0-9a-f]+)?$"
28 - arm,cci-400
29 - arm,cci-500
30 - arm,cci-550
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| /kernel/linux/linux-5.10/arch/mips/kernel/ |
| D | smp-cps.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include <asm/mips-cps.h>
20 #include <asm/pm-cps.h>
22 #include <asm/smp-cps.h>
38 static unsigned core_vpe_count(unsigned int cluster, unsigned core) in core_vpe_count() argument
43 return mips_cps_numvps(cluster, core); in core_vpe_count()
69 /* Use the number of VPEs in cluster 0 core 0 for smp_num_siblings */ in cps_smp_setup()
73 for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) { in cps_smp_setup()
112 /* If we have an FPU, enroll ourselves in the FPU-full mask */ in cps_smp_setup()
126 /* Detect whether the CCA is unsuited to multi-core SMP */ in cps_prepare_cpus()
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| /kernel/linux/linux-6.6/arch/mips/kernel/ |
| D | smp-cps.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
18 #include <asm/mips-cps.h>
21 #include <asm/pm-cps.h>
24 #include <asm/smp-cps.h>
32 static unsigned __init core_vpe_count(unsigned int cluster, unsigned core) in core_vpe_count() argument
34 return min(smp_max_threads, mips_cps_numvps(cluster, core)); in core_vpe_count()
60 /* Use the number of VPEs in cluster 0 core 0 for smp_num_siblings */ in cps_smp_setup()
64 for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) { in cps_smp_setup()
103 /* If we have an FPU, enroll ourselves in the FPU-full mask */ in cps_smp_setup()
117 /* Detect whether the CCA is unsuited to multi-core SMP */ in cps_prepare_cpus()
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,spm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
20 - enum:
21 - qcom,sdm660-gold-saw2-v4.1-l2
22 - qcom,sdm660-silver-saw2-v4.1-l2
23 - qcom,msm8998-gold-saw2-v4.1-l2
24 - qcom,msm8998-silver-saw2-v4.1-l2
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| /kernel/linux/linux-5.10/fs/exfat/ |
| D | exfat_fs.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2012-2013 Samsung Electronics Co., Ltd.
68 #define MAX_CHARSET_SIZE 6 /* max size of multi-byte character */
75 #define EXFAT_HINT_NONE -1
79 * helpers for cluster size to byte conversion.
81 #define EXFAT_CLU_TO_B(b, sbi) ((b) << (sbi)->cluster_size_bits)
82 #define EXFAT_B_TO_CLU(b, sbi) ((b) >> (sbi)->cluster_size_bits)
84 (((b - 1) >> (sbi)->cluster_size_bits) + 1)
85 #define EXFAT_CLU_OFFSET(off, sbi) ((off) & ((sbi)->cluster_size - 1))
90 #define EXFAT_BLK_TO_B(b, sb) ((b) << (sb)->s_blocksize_bits)
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| /kernel/linux/linux-6.6/fs/exfat/ |
| D | exfat_fs.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2012-2013 Samsung Electronics Co., Ltd.
51 (ES_IDX_FIRST_FILENAME + EXFAT_FILENAME_ENTRY_NUM(name_len) - 1)
77 #define MAX_CHARSET_SIZE 6 /* max size of multi-byte character */
81 #define EXFAT_HINT_NONE -1
85 * helpers for cluster size to byte conversion.
87 #define EXFAT_CLU_TO_B(b, sbi) ((b) << (sbi)->cluster_size_bits)
88 #define EXFAT_B_TO_CLU(b, sbi) ((b) >> (sbi)->cluster_size_bits)
90 (((b - 1) >> (sbi)->cluster_size_bits) + 1)
91 #define EXFAT_CLU_OFFSET(off, sbi) ((off) & ((sbi)->cluster_size - 1))
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | cci.txt | 5 ARM multi-cluster systems maintain intra-cluster coherency through a
24 - compatible
28 "arm,cci-400"
29 "arm,cci-500"
30 "arm,cci-550"
32 - reg
40 - ranges:
53 - CCI control interface nodes
55 Node name must be "slave-if".
61 - compatible
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