Searched +full:multi +full:- +full:configurable (Results 1 – 25 of 196) sorted by relevance
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| /kernel/linux/linux-5.10/Documentation/networking/device_drivers/ethernet/neterion/ |
| D | vxge.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 3) Configurable driver parameters
20 The X3100 series supports four modes of operation, configurable via
23 - Single function mode
24 - Multi function mode
25 - SRIOV mode
26 - MRIOV mode
28 The functions share a 10GbE link and the pci-e bus, but hardly anything else
40 ii) Multi function mode (up to 17 functions)
42 iii) PCI-SIG's I/O Virtualization
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/ |
| D | renesas,mtu2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Multi-Function Timer Pulse Unit 2 (MTU2)
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
14 The MTU2 is a multi-purpose, multi-channel timer/counter with configurable clock inputs
23 - enum:
24 - renesas,mtu2-r7s72100 # RZ/A1H
25 - const: renesas,mtu2
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/timer/ |
| D | renesas,mtu2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Multi-Function Timer Pulse Unit 2 (MTU2)
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
14 The MTU2 is a multi-purpose, multi-channel timer/counter with configurable clock inputs
23 - enum:
24 - renesas,mtu2-r7s72100 # RZ/A1H
25 - const: renesas,mtu2
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| /kernel/linux/linux-6.6/arch/sh/mm/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
9 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
12 On other systems (such as the SH-3 and 4) where an MMU exists,
64 configurable.
77 bool "Support 32-bit physical addressing through PMB"
83 32-bits through the SH-4A PMB. If this is not set, legacy
84 29-bit physical addressing will be used.
104 bool "Non-Uniform Memory Access (NUMA) Support"
163 This enables 8kB pages as supported by SH-X2 and later MMUs.
169 This enables 16kB pages on MMU-less SH systems.
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| /kernel/linux/linux-5.10/arch/sh/mm/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
9 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
12 On other systems (such as the SH-3 and 4) where an MMU exists,
68 configurable.
81 bool "Support 32-bit physical addressing through PMB"
87 32-bits through the SH-4A PMB. If this is not set, legacy
88 29-bit physical addressing will be used.
175 This enables 8kB pages as supported by SH-X2 and later MMUs.
181 This enables 16kB pages on MMU-less SH systems.
187 This enables support for 64kB pages, possible on all SH-4
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| /kernel/linux/linux-5.10/Documentation/block/ |
| D | null_blk.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 block-layer implementations. It emulates a block device of X gigabytes in size.
15 Multi-queue block-layer
17 - Request-based.
18 - Configurable submission queues per device.
20 No block-layer (Known as bio-based)
22 - Bio-based. IO requests are submitted directly to the device driver.
23 - Directly accepts bio data structure and returns them.
30 queue_mode=[0-2]: Default: 2-Multi-queue
31 Selects which block-layer the module should instantiate with.
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| /kernel/linux/linux-5.10/net/sched/ |
| D | sch_hhf.c | 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* net/sched/sch_hhf.c Heavy-Hitter Filter (HHF)
16 /* Heavy-Hitter Filter (HHF)
19 * Flows are classified into two buckets: non-heavy-hitter and heavy-hitter
20 * buckets. Initially, a new flow starts as non-heavy-hitter. Once classified
21 * as heavy-hitter, it is immediately switched to the heavy-hitter bucket.
23 * in which the heavy-hitter bucket is served with less weight.
24 * In other words, non-heavy-hitters (e.g., short bursts of critical traffic)
25 * are isolated from heavy-hitters (e.g., persistent bulk traffic) and also have
28 * To capture heavy-hitters, we use the "multi-stage filter" algorithm in the
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| /kernel/linux/linux-6.6/net/sched/ |
| D | sch_hhf.c | 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* net/sched/sch_hhf.c Heavy-Hitter Filter (HHF)
16 /* Heavy-Hitter Filter (HHF)
19 * Flows are classified into two buckets: non-heavy-hitter and heavy-hitter
20 * buckets. Initially, a new flow starts as non-heavy-hitter. Once classified
21 * as heavy-hitter, it is immediately switched to the heavy-hitter bucket.
23 * in which the heavy-hitter bucket is served with less weight.
24 * In other words, non-heavy-hitters (e.g., short bursts of critical traffic)
25 * are isolated from heavy-hitters (e.g., persistent bulk traffic) and also have
28 * To capture heavy-hitters, we use the "multi-stage filter" algorithm in the
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
25 To administer these schedulers, you'll need the user-level utilities
54 in-depth articles.
72 tristate "Multi Band Priority Queueing (PRIO)"
74 Say Y here if you want to use an n-band priority queue packet
81 tristate "Hardware Multiqueue-aware Multi Band Queuing (MULTIQ)"
83 Say Y here if you want to use an n-band queue packet scheduler
199 re-ordering. This is often useful to simulate networks when
219 tristate "Multi-queue priority scheduler (MQPRIO)"
222 Say Y here if you want to use the Multi-queue Priority scheduler.
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/ti/ |
| D | keystone-navigator-qmss.txt | 5 multi-core Navigator. QMSS consist of queue managers, packed-data structure
9 management of the packet queues. Packets are queued/de-queued by writing or
13 descriptor RAM. Descriptor RAM is configurable as internal or external memory.
20 - compatible : Must be "ti,keystone-navigator-qmss".
21 : Must be "ti,66ak2g-navss-qm" for QMSS on K2G SoC.
22 - clocks : phandle to the reference clock for this device.
23 - queue-range : <start number> total range of queue numbers for the device.
24 - linkram0 : <address size> for internal link ram, where size is the total
26 - linkram1 : <address size> for external link ram, where size is the total
29 - qmgrs : child node describing the individual queue managers on the
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/soc/ti/ |
| D | keystone-navigator-qmss.txt | 5 multi-core Navigator. QMSS consist of queue managers, packed-data structure
9 management of the packet queues. Packets are queued/de-queued by writing or
13 descriptor RAM. Descriptor RAM is configurable as internal or external memory.
20 - compatible : Must be "ti,keystone-navigator-qmss".
21 : Must be "ti,66ak2g-navss-qm" for QMSS on K2G SoC.
22 - clocks : phandle to the reference clock for this device.
23 - queue-range : <start number> total range of queue numbers for the device.
24 - linkram0 : <address size> for internal link ram, where size is the total
26 - linkram1 : <address size> for external link ram, where size is the total
29 - qmgrs : child node describing the individual queue managers on the
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| /kernel/linux/linux-5.10/Documentation/admin-guide/perf/ |
| D | arm-cmn.rst | 5 CMN-600 is a configurable mesh interconnect consisting of a rectangular
17 ----------
20 see /sys/bus/event_source/devices/arm_cmn_0. Multi-chip systems may link
21 more than one CMN together via external CCIX links - in this situation,
26 definitions - "type" selects the respective node type, and "eventid" the
30 * Since RN-D nodes do not have any distinct events from RN-I nodes, they
48 -----------
61 REQ or SNP channel, it can be specified as two events - one for each
62 group - with the same nonzero "combine" value. The count for such a
|
| /kernel/linux/linux-6.6/Documentation/admin-guide/perf/ |
| D | arm-cmn.rst | 5 CMN-600 is a configurable mesh interconnect consisting of a rectangular
17 ----------
20 see /sys/bus/event_source/devices/arm_cmn_0. Multi-chip systems may link
21 more than one CMN together via external CCIX links - in this situation,
26 definitions - "type" selects the respective node type, and "eventid" the
30 * Since RN-D nodes do not have any distinct events from RN-I nodes, they
48 -----------
61 REQ or SNP channel, it can be specified as two events - one for each
62 group - with the same nonzero "combine" value. The count for such a
|
| /kernel/linux/linux-6.6/Documentation/block/ |
| D | null_blk.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 block-layer implementations. It emulates a block device of X gigabytes in size.
15 Multi-queue block-layer
17 - Request-based.
18 - Configurable submission queues per device.
20 No block-layer (Known as bio-based)
22 - Bio-based. IO requests are submitted directly to the device driver.
23 - Directly accepts bio data structure and returns them.
30 queue_mode=[0-2]: Default: 2-Multi-queue
31 Selects which block-layer the module should instantiate with.
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/ |
| D | trivial-devices.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/trivial-devices.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
27 spi-max-frequency: true
31 - enum:
33 - acbel,fsg032
34 … # SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
35 - ad,ad7414
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/iommu/ |
| D | iommu.txt | 13 Example: 32-bit DMA to 64-bit physical addresses
15 * Implement scatter-gather at page level granularity so that the device does
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
30 typically have a fixed association to the master device, whereas multiple-
34 "dma-ranges" property that describes how the physical address space of the
35 IOMMU maps to memory. An empty "dma-ranges" property means that there is a
39 --------------------
40 - #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
44 the specific IOMMU. Below are a few examples of typical use-cases:
46 - #iommu-cells = <0>: Single master IOMMU devices are not configurable and
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| /kernel/linux/linux-6.6/Documentation/arch/arm/keystone/ |
| D | knav-qmss.rst | 11 multi-core Navigator. QMSS consist of queue managers, packed-data structure
15 management of the packet queues. Packets are queued/de-queued by writing or
19 descriptor RAM. Descriptor RAM is configurable as internal or external memory.
29 Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt
40 git://git.ti.com/keystone-rtos/qmss-lld.git
43 channels. This firmware is available under ti-keystone folder of
46 git://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git
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| /kernel/linux/linux-5.10/Documentation/arm/keystone/ |
| D | knav-qmss.rst | 11 multi-core Navigator. QMSS consist of queue managers, packed-data structure
15 management of the packet queues. Packets are queued/de-queued by writing or
19 descriptor RAM. Descriptor RAM is configurable as internal or external memory.
29 Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt
40 git://git.ti.com/keystone-rtos/qmss-lld.git
43 channels. This firmware is available under ti-keystone folder of
46 git://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/iommu/ |
| D | iommu.txt | 13 Example: 32-bit DMA to 64-bit physical addresses
15 * Implement scatter-gather at page level granularity so that the device does
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
30 typically have a fixed association to the master device, whereas multiple-
34 "dma-ranges" property that describes how the physical address space of the
35 IOMMU maps to memory. An empty "dma-ranges" property means that there is a
39 --------------------
40 - #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
44 the specific IOMMU. Below are a few examples of typical use-cases:
46 - #iommu-cells = <0>: Single master IOMMU devices are not configurable and
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mfd/ |
| D | ti,tps6594.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Julien Panis <jpanis@baylibre.com>
15 PFSM (Pre-configurable Finite State Machine) managing the state of the device.
16 TPS6594 is the super-set device while TPS6593 and LP8764 are derivatives.
21 - ti,lp8764-q1
22 - ti,tps6593-q1
23 - ti,tps6594-q1
29 ti,primary-pmic:
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/regulator/ |
| D | richtek,rtq2208.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alina Yu <alina_yu@richtek.com>
14 multi-configurable synchronous buck converters and two LDOs.
16 Bucks support "regulator-allowed-modes" and "regulator-mode". The former defines the permitted
25 0 - Auto mode for power saving, which reducing the switching frequency at light load condition
27 …1 - FCCM to meet the strict voltage regulation accuracy, which keeping constant switching frequenc…
35 - richtek,rtq2208
43 richtek,mtp-sel-high:
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| /kernel/linux/linux-6.6/sound/soc/tegra/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "SoC Audio for the Tegra System-on-Chip"
82 Config to enable the Inter-IC Sound (I2S) Controller which
83 implements full-duplex and bidirectional and single direction
84 point-to-point serial interfaces. It can interface with I2S
92 Parametric Equalizer (PEQ) and Multi Band Dynamic Range Compressor
113 converts the multi-bit Pulse Code Modulation (PCM) audio input to
114 oversampled 1-bit Pulse Density Modulation (PDM) output. From the
116 that up-samples the input to the desired sampling rate by
118 the desired 1-bit output via Delta Sigma Modulation (DSM).
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| /kernel/linux/linux-6.6/drivers/regulator/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
38 managed regulators and simple non-configurable regulators.
65 They provide two I2C-controlled DC/DC step-down converters with
85 tristate "Active-semi act8865 voltage regulator"
90 This driver controls a active-semi act8865 voltage output
94 tristate "Active-semi ACT8945A voltage regulator"
97 This driver controls a active-semi ACT8945A voltage regulator
98 via I2C bus. The ACT8945A features three step-down DC/DC converters
99 and four low-dropout linear regulators, along with a ActivePath
110 tristate "Freescale i.MX on-chip ANATOP LDO regulators"
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/ |
| D | renesas,rza1-ports.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacopo Mondi <jacopo+renesas@jmondi.org>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis
17 writing configuration values to per-port register sets.
18 Each "port" features up to 16 pins, each of them configurable for GPIO
25 - const: renesas,r7s72100-ports # RZ/A1H
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | renesas,rza1-ports.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacopo Mondi <jacopo+renesas@jmondi.org>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis
17 writing configuration values to per-port register sets.
18 Each "port" features up to 16 pins, each of them configurable for GPIO
25 - const: renesas,r7s72100-ports # RZ/A1H
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