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/kernel/linux/linux-6.6/drivers/mtd/nand/
Decc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Generic Error-Correcting Code (ECC) engine
10 * This file describes the abstraction of any NAND ECC engine. It has been
11 * designed to fit most cases, including parallel NANDs and SPI-NANDs.
13 * There are three main situations where instantiating this ECC engine makes
15 * - external: The ECC engine is outside the NAND pipeline, typically this
16 * is a software ECC engine, or an hardware engine that is
17 * outside the NAND controller pipeline.
18 * - pipelined: The ECC engine is inside the NAND pipeline, ie. on the
19 * controller's side. This is the case of most of the raw NAND
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/
Dnand-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NAND Chip and NAND Controller Generic Binding
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This representation should be
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Dnvidia-tegra20-nand.txt1 NVIDIA Tegra NAND Flash controller
4 - compatible: Must be one of:
5 - "nvidia,tegra20-nand"
6 - reg: MMIO address range
7 - interrupts: interrupt output of the NFC controller
8 - clocks: Must contain an entry for each entry in clock-names.
9 See ../clocks/clock-bindings.txt for details.
10 - clock-names: Must include the following entries:
11 - nand
12 - resets: Must contain an entry for each entry in reset-names.
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Dallwinner,sun4i-a10-nand.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/allwinner,sun4i-a10-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 NAND Controller Device Tree Bindings
10 - $ref: "nand-controller.yaml"
13 - Chen-Yu Tsai <wens@csie.org>
14 - Maxime Ripard <mripard@kernel.org>
17 "#address-cells": true
18 "#size-cells": true
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Doxnas-nand.txt1 * Oxford Semiconductor OXNAS NAND Controller
3 Please refer to nand-controller.yaml for generic information regarding MTD NAND bindings.
6 - compatible: "oxsemi,ox820-nand"
7 - reg: Base address and length for NAND mapped memory.
10 - clocks: phandle to the NAND gate clock if needed.
11 - resets: phandle to the NAND reset control if needed.
15 nandc: nand-controller@41000000 {
16 compatible = "oxsemi,ox820-nand";
20 #address-cells = <1>;
21 #size-cells = <0>;
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Dmarvell-nand.txt1 Marvell NAND Flash Controller (NFC)
4 - compatible: can be one of the following:
5 * "marvell,armada-8k-nand-controller"
6 * "marvell,armada370-nand-controller"
7 * "marvell,pxa3xx-nand-controller"
8 * "marvell,armada-8k-nand" (deprecated)
9 * "marvell,armada370-nand" (deprecated)
10 * "marvell,pxa3xx-nand" (deprecated)
13 - reg: NAND flash controller memory area.
14 - #address-cells: shall be set to 1. Encode the NAND CS.
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Dmxic-nand.txt1 Macronix Raw NAND Controller Device Tree Bindings
2 -------------------------------------------------
5 - compatible: should be "mxic,multi-itfc-v009-nand-controller"
6 - reg: should contain 1 entry for the registers
7 - #address-cells: should be set to 1
8 - #size-cells: should be set to 0
9 - interrupts: interrupt line connected to this raw NAND controller
10 - clock-names: should contain "ps", "send" and "send_dly"
11 - clocks: should contain 3 phandles for the "ps", "send" and
15 - children nodes represent the available NAND chips.
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mtd/
Dnvidia-tegra20-nand.txt1 NVIDIA Tegra NAND Flash controller
4 - compatible: Must be one of:
5 - "nvidia,tegra20-nand"
6 - reg: MMIO address range
7 - interrupts: interrupt output of the NFC controller
8 - clocks: Must contain an entry for each entry in clock-names.
9 See ../clocks/clock-bindings.txt for details.
10 - clock-names: Must include the following entries:
11 - nand
12 - resets: Must contain an entry for each entry in reset-names.
[all …]
Dnand-chip.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NAND Chip Common Properties
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: mtd.yaml#
16 This file covers the generic description of a NAND chip. It implies that the
17 bus interface should not be taken into account: both raw NAND devices and
18 SPI-NAND devices are concerned by this description.
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Dmxic-nand.txt1 Macronix Raw NAND Controller Device Tree Bindings
2 -------------------------------------------------
5 - compatible: should be "mxic,multi-itfc-v009-nand-controller"
6 - reg: should contain 1 entry for the registers
7 - #address-cells: should be set to 1
8 - #size-cells: should be set to 0
9 - interrupts: interrupt line connected to this raw NAND controller
10 - clock-names: should contain "ps", "send" and "send_dly"
11 - clocks: should contain 3 phandles for the "ps", "send" and
15 - children nodes represent the available NAND chips.
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/kernel/linux/linux-5.10/drivers/mtd/nand/raw/
Dtegra_nand.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2014-2015 Lucas Stach <dev@lynxeye.de>
10 #include <linux/dma-mapping.h>
31 #define COMMAND_TRANS_SIZE(size) ((((size) - 1) & 0xf) << 20)
37 #define COMMAND_CLE_SIZE(size) ((((size) - 1) & 0x3) << 4)
38 #define COMMAND_ALE_SIZE(size) ((((size) - 1) & 0xf) << 0)
153 #define OFFSET(val, off) ((val) < (off) ? 0 : (val) - (off))
182 struct mtd_oob_region ecc; member
204 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_RS * chip->ecc.strength, in tegra_nand_ooblayout_rs_ecc()
208 return -ERANGE; in tegra_nand_ooblayout_rs_ecc()
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Dplat_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Generic NAND driver
24 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT && in plat_nand_attach_chip()
25 chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) in plat_nand_attach_chip()
26 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; in plat_nand_attach_chip()
36 * Probe for the NAND device.
40 struct platform_nand_data *pdata = dev_get_platdata(&pdev->dev); in plat_nand_probe()
48 dev_err(&pdev->dev, "platform_nand_data is missing\n"); in plat_nand_probe()
49 return -EINVAL; in plat_nand_probe()
52 if (pdata->chip.nr_chips < 1) { in plat_nand_probe()
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Dsocrates_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
32 * socrates_nand_write_buf - write buffer to chip
33 * @this: NAND chip object
44 out_be32(host->io_base, FPGA_NAND_ENABLE | in socrates_nand_write_buf()
51 * socrates_nand_read_buf - read chip data into buffer
52 * @this: NAND chip object
65 out_be32(host->io_base, val); in socrates_nand_read_buf()
67 buf[i] = (in_be32(host->io_base) >> in socrates_nand_read_buf()
73 * socrates_nand_read_byte - read one byte from the chip
84 * Hardware specific access to control-lines
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Dpasemi_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2006-2007 PA Semi, Inc
8 * Driver for the PWRficient onchip NAND flash interface
33 static const char driver_name[] = "pasemi-nand";
38 memcpy_fromio(buf, chip->legacy.IO_ADDR_R, 0x800); in pasemi_read_buf()
40 len -= 0x800; in pasemi_read_buf()
42 memcpy_fromio(buf, chip->legacy.IO_ADDR_R, len); in pasemi_read_buf()
49 memcpy_toio(chip->legacy.IO_ADDR_R, buf, 0x800); in pasemi_write_buf()
51 len -= 0x800; in pasemi_write_buf()
53 memcpy_toio(chip->legacy.IO_ADDR_R, buf, len); in pasemi_write_buf()
[all …]
/kernel/linux/linux-6.6/drivers/mtd/nand/raw/
Dtegra_nand.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2014-2015 Lucas Stach <dev@lynxeye.de>
10 #include <linux/dma-mapping.h>
34 #define COMMAND_TRANS_SIZE(size) ((((size) - 1) & 0xf) << 20)
40 #define COMMAND_CLE_SIZE(size) ((((size) - 1) & 0x3) << 4)
41 #define COMMAND_ALE_SIZE(size) ((((size) - 1) & 0xf) << 0)
156 #define OFFSET(val, off) ((val) < (off) ? 0 : (val) - (off))
185 struct mtd_oob_region ecc; member
207 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_RS * chip->ecc.strength, in tegra_nand_ooblayout_rs_ecc()
211 return -ERANGE; in tegra_nand_ooblayout_rs_ecc()
[all …]
Dplat_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Generic NAND driver
24 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT && in plat_nand_attach_chip()
25 chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) in plat_nand_attach_chip()
26 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; in plat_nand_attach_chip()
36 * Probe for the NAND device.
40 struct platform_nand_data *pdata = dev_get_platdata(&pdev->dev); in plat_nand_probe()
47 dev_err(&pdev->dev, "platform_nand_data is missing\n"); in plat_nand_probe()
48 return -EINVAL; in plat_nand_probe()
51 if (pdata->chip.nr_chips < 1) { in plat_nand_probe()
[all …]
Dsocrates_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
33 * socrates_nand_write_buf - write buffer to chip
34 * @this: NAND chip object
45 out_be32(host->io_base, FPGA_NAND_ENABLE | in socrates_nand_write_buf()
52 * socrates_nand_read_buf - read chip data into buffer
53 * @this: NAND chip object
66 out_be32(host->io_base, val); in socrates_nand_read_buf()
68 buf[i] = (in_be32(host->io_base) >> in socrates_nand_read_buf()
74 * socrates_nand_read_byte - read one byte from the chip
85 * Hardware specific access to control-lines
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Dxway_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright © 2016 Hauke Mehrtens <hauke@hauke-m.de>
15 /* nand registers */
19 #define NAND_WAIT_RD BIT(0) /* NAND flash status output */
20 #define NAND_WAIT_WR_C BIT(3) /* NAND Write/Read complete */
25 * nand commands
26 * The pins of the NAND chip are selected based on the address bits of the
42 /* we need to tel the ebu which addr we mapped the nand to */
46 /* we need to tell the EBU that we have nand attached and set it up properly */
77 return readb(data->nandaddr + op); in xway_readb()
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/kernel/linux/linux-6.6/arch/arm/boot/dts/broadcom/
Dbcm5301x-nand-cs0-bch8.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Broadcom BCM470X / BCM5301X Nand chip defaults.
5 * This should be included if the NAND controller is on chip select 0
6 * and uses 8 bit ECC.
8 * Copyright (C) 2015 Hauke Mehrtens <hauke@hauke-m.de>
11 #include "bcm5301x-nand-cs0.dtsi"
14 nand-ecc-algo = "bch";
15 nand-ecc-strength = <8>;
16 nand-ecc-step-size = <512>;
Dbcm5301x-nand-cs0-bch1.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Broadcom Northstar NAND.
8 #include "bcm5301x-nand-cs0.dtsi"
11 nand-ecc-algo = "bch";
12 nand-ecc-strength = <1>;
13 nand-ecc-step-size = <512>;
Dbcm5301x-nand-cs0-bch4.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 #include "bcm5301x-nand-cs0.dtsi"
9 nand-ecc-algo = "bch";
10 nand-ecc-strength = <4>;
11 nand-ecc-step-size = <512>;
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dbcm5301x-nand-cs0-bch8.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Broadcom BCM470X / BCM5301X Nand chip defaults.
5 * This should be included if the NAND controller is on chip select 0
6 * and uses 8 bit ECC.
8 * Copyright (C) 2015 Hauke Mehrtens <hauke@hauke-m.de>
11 #include "bcm5301x-nand-cs0.dtsi"
14 nand-ecc-algo = "bch";
15 nand-ecc-strength = <8>;
16 nand-ecc-step-size = <512>;
Dbcm5301x-nand-cs0-bch1.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Broadcom Northstar NAND.
8 #include "bcm5301x-nand-cs0.dtsi"
11 nand-ecc-algo = "bch";
12 nand-ecc-strength = <1>;
13 nand-ecc-step-size = <512>;
Dbcm5301x-nand-cs0-bch4.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 #include "bcm5301x-nand-cs0.dtsi"
9 nand-ecc-algo = "bch";
10 nand-ecc-strength = <4>;
11 nand-ecc-step-size = <512>;
/kernel/linux/linux-5.10/drivers/mtd/nand/
Decc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Generic Error-Correcting Code (ECC) engine
10 * This file describes the abstraction of any NAND ECC engine. It has been
11 * designed to fit most cases, including parallel NANDs and SPI-NANDs.
13 * There are three main situations where instantiating this ECC engine makes
15 * - external: The ECC engine is outside the NAND pipeline, typically this
16 * is a software ECC engine, or an hardware engine that is
17 * outside the NAND controller pipeline.
18 * - pipelined: The ECC engine is inside the NAND pipeline, ie. on the
19 * controller's side. This is the case of most of the raw NAND
[all …]

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