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Searched full:nand_x_clk (Results 1 – 12 of 12) sorted by relevance

/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dsocfpga_arria10.dtsi371 nand_x_clk: nand_x_clk { label
381 clocks = <&nand_x_clk>;
388 clocks = <&nand_x_clk>;
673 clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
Dsocfpga.dtsi469 nand_x_clk: nand_x_clk { label
479 clocks = <&nand_x_clk>;
486 clocks = <&nand_x_clk>;
773 clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
/kernel/linux/linux-6.6/arch/arm/boot/dts/intel/socfpga/
Dsocfpga_arria10.dtsi377 nand_x_clk: nand_x_clk { label
387 clocks = <&nand_x_clk>;
394 clocks = <&nand_x_clk>;
680 clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
Dsocfpga.dtsi466 nand_x_clk: nand_x_clk { label
476 clocks = <&nand_x_clk>;
483 clocks = <&nand_x_clk>;
779 clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
/kernel/linux/linux-6.6/drivers/clk/socfpga/
Dclk-s10.c298 { STRATIX10_NAND_X_CLK, "nand_x_clk", "l4_mp_clk", NULL, 1, 0, 0xA4,
300 { STRATIX10_NAND_CLK, "nand_clk", "nand_x_clk", NULL, 1, 0, 0xA4,
302 { STRATIX10_NAND_ECC_CLK, "nand_ecc_clk", "nand_x_clk", NULL, 1, 0, 0xA4,
Dclk-agilex.c329 { AGILEX_NAND_X_CLK, "nand_x_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
331 { AGILEX_NAND_CLK, "nand_clk", "nand_x_clk", NULL, 1, 0, 0x7C,
333 { AGILEX_NAND_ECC_CLK, "nand_ecc_clk", "nand_x_clk", NULL, 1, 0, 0x7C,
Dclk-gate.c20 #define SOCFPGA_NAND_X_CLK "nand_x_clk"
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mtd/
Ddenali,nand.yaml144 clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/
Ddenali,nand.yaml141 clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
/kernel/linux/linux-5.10/drivers/clk/socfpga/
Dclk-agilex.c317 { AGILEX_NAND_X_CLK, "nand_x_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
319 { AGILEX_NAND_CLK, "nand_clk", "nand_x_clk", NULL, 1, 0, 0x7C,
321 { AGILEX_NAND_ECC_CLK, "nand_ecc_clk", "nand_x_clk", NULL, 1, 0, 0x7C,
Dclk-s10.c299 { STRATIX10_NAND_X_CLK, "nand_x_clk", "l4_mp_clk", NULL, 1, 0, 0xA4,
301 { STRATIX10_NAND_CLK, "nand_clk", "nand_x_clk", NULL, 1, 0, 0xA4,
303 { STRATIX10_NAND_ECC_CLK, "nand_ecc_clk", "nand_x_clk", NULL, 1, 0, 0xA4,
Dclk-gate.c20 #define SOCFPGA_NAND_X_CLK "nand_x_clk"