| /kernel/linux/linux-6.6/drivers/clk/ingenic/ |
| D | cgu.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (c) 2013-2015 Imagination Technologies
13 #include <linux/clk-provider.h>
18 * struct ingenic_cgu_pll_info - information about a PLL
27 * @n_shift: the number of bits to shift the divider value by (ie. the
28 * index of the lowest bit of the divider value in the PLL's
30 * @n_bits: the size of the divider field in bits
31 * @n_offset: the divider value which encodes to 0 in the PLL's control
33 * @od_shift: the number of bits to shift the post-VCO divider value by (ie.
34 * the index of the lowest bit of the post-VCO divider value in
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/baikal-t1/ |
| D | ccu-div.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Baikal-T1 CCU Dividers interface driver
10 #include <linux/clk-provider.h>
17 * CCU Divider private clock IDs
21 #define CCU_SYS_SATA_CLK -1
22 #define CCU_SYS_XGMAC_CLK -2
25 * CCU Divider private flags
26 * @CCU_DIV_SKIP_ONE: Due to some reason divider can't be set to 1.
28 * @CCU_DIV_SKIP_ONE_TO_THREE: For some reason divider can't be within [1,3].
30 * @CCU_DIV_LOCK_SHIFTED: Find lock-bit at non-standard position.
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| /kernel/linux/linux-6.6/drivers/clk/baikal-t1/ |
| D | ccu-div.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Baikal-T1 CCU Dividers interface driver
10 #include <linux/clk-provider.h>
17 * CCU Divider private clock IDs
21 #define CCU_SYS_SATA_CLK -1
22 #define CCU_SYS_XGMAC_CLK -2
25 * CCU Divider private flags
26 * @CCU_DIV_BASIC: Basic divider clock required by the kernel as early as
28 * @CCU_DIV_SKIP_ONE: Due to some reason divider can't be set to 1.
30 * @CCU_DIV_SKIP_ONE_TO_THREE: For some reason divider can't be within [1,3].
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/bcm/ |
| D | clk-kona.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
16 #include <linux/clk-provider.h>
24 #define BAD_CLK_NAME ((const char *)-1)
33 #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
34 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
35 #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
36 #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
40 #define ccu_policy_exists(ccu_policy) ((ccu_policy)->enable.offset != 0)
44 #define policy_exists(policy) ((policy)->offset != 0)
55 #define hyst_exists(hyst) ((hyst)->offset != 0)
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| D | clk-kona.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "clk-kona.h"
12 #include <linux/clk-provider.h>
27 /* Produces a mask of set bits covering a range of a 32-bit value */
30 return ((1 << width) - 1) << shift; in bitfield_mask()
47 /* Divider and scaling helpers */
49 /* Convert a divider into the scaled divisor value it represents. */
52 return (u64)reg_div + ((u64)1 << div->u.s.frac_width); in scaled_div_value()
56 * Build a scaled divider value as close as possible to the
68 combined <<= div->u.s.frac_width; in scaled_div_build()
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| /kernel/linux/linux-5.10/drivers/clk/bcm/ |
| D | clk-kona.h | 24 #include <linux/clk-provider.h>
32 #define BAD_CLK_NAME ((const char *)-1)
41 #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
42 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
43 #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
44 #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
48 #define ccu_policy_exists(ccu_policy) ((ccu_policy)->enable.offset != 0)
52 #define policy_exists(policy) ((policy)->offset != 0)
63 #define hyst_exists(hyst) ((hyst)->offset != 0)
68 (div)->u.s.frac_width > 0)
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| D | clk-kona.c | 15 #include "clk-kona.h"
20 #include <linux/clk-provider.h>
35 /* Produces a mask of set bits covering a range of a 32-bit value */
38 return ((1 << width) - 1) << shift; in bitfield_mask()
55 /* Divider and scaling helpers */
57 /* Convert a divider into the scaled divisor value it represents. */
60 return (u64)reg_div + ((u64)1 << div->u.s.frac_width); in scaled_div_value()
64 * Build a scaled divider value as close as possible to the
76 combined <<= div->u.s.frac_width; in scaled_div_build()
81 /* The scaled minimum divisor representable by a divider */
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/ti/ |
| D | divider.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI Divider Clock
7 * Tero Kristo <t-kristo@ti.com>
10 #include <linux/clk-provider.h>
26 for (clkt = table; clkt->div; clkt++) in _get_table_div()
27 if (clkt->val == val) in _get_table_div()
28 return clkt->div; in _get_table_div()
32 static void _setup_mask(struct clk_omap_divider *divider) in _setup_mask() argument
38 if (divider->table) { in _setup_mask()
41 for (clkt = divider->table; clkt->div; clkt++) in _setup_mask()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/ti/ |
| D | divider.c | 2 * TI Divider Clock
6 * Tero Kristo <t-kristo@ti.com>
18 #include <linux/clk-provider.h>
34 for (clkt = table; clkt->div; clkt++) in _get_table_div()
35 if (clkt->val == val) in _get_table_div()
36 return clkt->div; in _get_table_div()
40 static void _setup_mask(struct clk_omap_divider *divider) in _setup_mask() argument
46 if (divider->table) { in _setup_mask()
49 for (clkt = divider->table; clkt->div; clkt++) in _setup_mask()
50 if (clkt->val > max_val) in _setup_mask()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/ingenic/ |
| D | cgu.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (c) 2013-2015 Imagination Technologies
13 #include <linux/clk-provider.h>
18 * struct ingenic_cgu_pll_info - information about a PLL
27 * @n_shift: the number of bits to shift the divider value by (ie. the
28 * index of the lowest bit of the divider value in the PLL's
30 * @n_bits: the size of the divider field in bits
31 * @n_offset: the divider value which encodes to 0 in the PLL's control
33 * @od_shift: the number of bits to shift the post-VCO divider value by (ie.
34 * the index of the lowest bit of the post-VCO divider value in
[all …]
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| /kernel/linux/linux-5.10/drivers/media/i2c/cx25840/ |
| D | cx25840-ir.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <media/drv-intf/cx25840.h>
14 #include <media/rc-core.h>
16 #include "cx25840-core.h"
117 return state ? state->ir_state : NULL; in to_ir_state()
122 * Rx and Tx Clock Divider register computations
124 * Note the largest clock divider value of 0xffff corresponds to:
135 d--; in count_to_clock_divider()
145 static inline unsigned int clock_divider_to_ns(unsigned int divider) in clock_divider_to_ns() argument
148 return DIV_ROUND_CLOSEST((divider + 1) * 1000, in clock_divider_to_ns()
[all …]
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| /kernel/linux/linux-6.6/drivers/media/i2c/cx25840/ |
| D | cx25840-ir.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <media/drv-intf/cx25840.h>
14 #include <media/rc-core.h>
16 #include "cx25840-core.h"
117 return state ? state->ir_state : NULL; in to_ir_state()
122 * Rx and Tx Clock Divider register computations
124 * Note the largest clock divider value of 0xffff corresponds to:
135 d--; in count_to_clock_divider()
145 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) in clock_divider_to_carrier_freq() argument
147 return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, (divider + 1) * 16); in clock_divider_to_carrier_freq()
[all …]
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| /kernel/linux/linux-6.6/drivers/media/pci/cx23885/ |
| D | cx23888-ir.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include "cx23888-ir.h"
16 #include <media/v4l2-device.h>
17 #include <media/rc-core.h>
161 * Rx and Tx Clock Divider register computations
163 * Note the largest clock divider value of 0xffff corresponds to:
174 d--; in count_to_clock_divider()
184 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) in clock_divider_to_carrier_freq() argument
186 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16); in clock_divider_to_carrier_freq()
189 static inline unsigned int clock_divider_to_freq(unsigned int divider, in clock_divider_to_freq() argument
[all …]
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| /kernel/linux/linux-5.10/drivers/media/pci/cx23885/ |
| D | cx23888-ir.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include "cx23888-ir.h"
16 #include <media/v4l2-device.h>
17 #include <media/rc-core.h>
161 * Rx and Tx Clock Divider register computations
163 * Note the largest clock divider value of 0xffff corresponds to:
174 d--; in count_to_clock_divider()
184 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) in clock_divider_to_carrier_freq() argument
186 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16); in clock_divider_to_carrier_freq()
189 static inline unsigned int clock_divider_to_freq(unsigned int divider, in clock_divider_to_freq() argument
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/zynqmp/ |
| D | divider.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC Divider support
5 * Copyright (C) 2016-2019 Xilinx
7 * Adjustable divider clock implementation
11 #include <linux/clk-provider.h>
13 #include "clk-zynqmp.h"
16 * DOC: basic adjustable divider clock that cannot gate
19 * prepare - clk_prepare only ensures that parents are prepared
20 * enable - clk_enable only ensures that parents are enabled
21 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/zynqmp/ |
| D | divider.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC Divider support
5 * Copyright (C) 2016-2019 Xilinx
7 * Adjustable divider clock implementation
11 #include <linux/clk-provider.h>
13 #include "clk-zynqmp.h"
16 * DOC: basic adjustable divider clock that cannot gate
19 * prepare - clk_prepare only ensures that parents are prepared
20 * enable - clk_enable only ensures that parents are enabled
21 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | omap44xx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <59000000>;
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <12000000>;
21 #clock-cells = <0>;
22 compatible = "ti,gate-clock";
24 ti,bit-shift = <8>;
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| D | omap54xx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <12000000>;
15 #clock-cells = <0>;
16 compatible = "ti,gate-clock";
18 ti,bit-shift = <8>;
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <32768>;
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/ti/omap/ |
| D | omap44xx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "extalt_clkin_ck";
12 clock-frequency = <59000000>;
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-output-names = "pad_clks_src_ck";
19 clock-frequency = <12000000>;
23 #clock-cells = <0>;
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/imx/ |
| D | clk-divider-gate.c | 1 // SPDX-License-Identifier: GPL-2.0+
7 #include <linux/clk-provider.h>
15 struct clk_divider divider; member
23 return container_of(div, struct clk_divider_gate, divider); in to_clk_divider_gate()
32 val = readl(div->reg) >> div->shift; in clk_divider_gate_recalc_rate_ro()
33 val &= clk_div_mask(div->width); in clk_divider_gate_recalc_rate_ro()
37 return divider_recalc_rate(hw, parent_rate, val, div->table, in clk_divider_gate_recalc_rate_ro()
38 div->flags, div->width); in clk_divider_gate_recalc_rate_ro()
49 spin_lock_irqsave(div->lock, flags); in clk_divider_gate_recalc_rate()
52 val = div_gate->cached_val; in clk_divider_gate_recalc_rate()
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/imx/ |
| D | clk-divider-gate.c | 1 // SPDX-License-Identifier: GPL-2.0+
7 #include <linux/clk-provider.h>
15 struct clk_divider divider; member
23 return container_of(div, struct clk_divider_gate, divider); in to_clk_divider_gate()
32 val = readl(div->reg) >> div->shift; in clk_divider_gate_recalc_rate_ro()
33 val &= clk_div_mask(div->width); in clk_divider_gate_recalc_rate_ro()
37 return divider_recalc_rate(hw, parent_rate, val, div->table, in clk_divider_gate_recalc_rate_ro()
38 div->flags, div->width); in clk_divider_gate_recalc_rate_ro()
49 spin_lock_irqsave(div->lock, flags); in clk_divider_gate_recalc_rate()
52 val = div_gate->cached_val; in clk_divider_gate_recalc_rate()
[all …]
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| /kernel/linux/linux-6.6/arch/powerpc/boot/ |
| D | cuboot-acadia.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Old U-boot compatibility for Acadia
23 #define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
27 #define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
28 #define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
29 #define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
36 #define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */
37 #define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */
38 #define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */
39 #define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */
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| /kernel/linux/linux-5.10/arch/powerpc/boot/ |
| D | cuboot-acadia.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Old U-boot compatibility for Acadia
23 #define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
27 #define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
28 #define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
29 #define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
36 #define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */
37 #define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */
38 #define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */
39 #define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */
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| /kernel/linux/linux-5.10/drivers/clk/ |
| D | clk-divider.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
7 * Adjustable divider clock implementation
10 #include <linux/clk-provider.h>
19 * DOC: basic adjustable divider clock that cannot gate
22 * prepare - clk_prepare only ensures that parents are prepared
23 * enable - clk_enable only ensures that parents are enabled
24 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
25 * parent - fixed parent. No clk_set_parent support
28 static inline u32 clk_div_readl(struct clk_divider *divider) in clk_div_readl() argument
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/basics/ |
| D | conversion.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
28 #define DIVIDER 10000 macro
30 /* S2D13 value in [-3.00...0.9999] */
31 #define S2D13_MIN (-3 * DIVIDER)
32 #define S2D13_MAX (3 * DIVIDER)
48 if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor)) in fixed_point_to_int_frac()
87 dc_fixpt_from_fraction(S2D13_MIN, DIVIDER); in convert_float_matrix()
89 dc_fixpt_from_fraction(S2D13_MAX, DIVIDER); in convert_float_matrix()
|