Searched +full:no +full:- +full:mmc +full:- +full:hs400 (Results 1 – 25 of 118) sorted by relevance
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mmc/ |
| D | mtk-sd.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Chaotian Jing <chaotian.jing@mediatek.com> 11 - Wenbin Mei <wenbin.mei@mediatek.com> 16 - enum: 17 - mediatek,mt2701-mmc 18 - mediatek,mt2712-mmc 19 - mediatek,mt6779-mmc [all …]
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| D | mmc-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: MMC Controller Common Properties 10 - Ulf Hansson <ulf.hansson@linaro.org> 13 These properties are common to multiple MMC host controllers. Any host 17 It is possible to assign a fixed index mmcN to an MMC host controller 23 pattern: "^mmc(@.*)?$" 25 "#address-cells": [all …]
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| D | sdhci-sprd.txt | 1 * Spreadtrum SDHCI controller (sdhci-sprd) 4 for MMC, SD and SDIO types of cards. 6 This file documents differences between the core properties in mmc.txt 7 and the properties used by the sdhci-sprd driver. 10 - compatible: Should contain "sprd,sdhci-r11". 11 - reg: physical base address of the controller and length. 12 - interrupts: Interrupts used by the SDHCI controller. 13 - clocks: Should contain phandle for the clock feeding the SDHCI controller 14 - clock-names: Should contain the following: 15 "sdio" - SDIO source clock (required) [all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | sdhci-sprd.txt | 1 * Spreadtrum SDHCI controller (sdhci-sprd) 4 for MMC, SD and SDIO types of cards. 6 This file documents differences between the core properties in mmc.txt 7 and the properties used by the sdhci-sprd driver. 10 - compatible: Should contain "sprd,sdhci-r11". 11 - reg: physical base address of the controller and length. 12 - interrupts: Interrupts used by the SDHCI controller. 13 - clocks: Should contain phandle for the clock feeding the SDHCI controller 14 - clock-names: Should contain the following: 15 "sdio" - SDIO source clock (required) [all …]
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| D | mmc-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: MMC Controller Generic Binding 10 - Ulf Hansson <ulf.hansson@linaro.org> 13 These properties are common to multiple MMC host controllers. Any host 17 It is possible to assign a fixed index mmcN to an MMC host controller 23 pattern: "^mmc(@.*)?$" 25 "#address-cells": [all …]
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| D | exynos-dw-mshc.txt | 5 a SoC with storage medium such as eMMC or SD/MMC cards. This file documents 7 by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific 13 - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210 15 - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412 17 - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250 19 - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420 21 - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7 23 - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7 26 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface 30 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value [all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/mediatek/ |
| D | mt7986a-bananapi-bpi-r3-emmc.dtso | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 7 /dts-v1/; 11 compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; 14 target-path = "/soc/mmc@11230000"; 16 bus-width = <8>; 17 max-frequency = <200000000>; 18 cap-mmc-highspeed; 19 mmc-hs200-1_8v; 20 mmc-hs400-1_8v; 21 hs400-ds-delay = <0x14014>; [all …]
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| D | mt8183-pumpkin.dts | 1 // SPDX-License-Identifier: GPL-2.0 7 /dts-v1/; 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/input/input.h> 16 compatible = "mediatek,mt8183-pumpkin", "mediatek,mt8183"; 28 stdout-path = "serial0:921600n8"; 31 reserved-memory { 32 #address-cells = <2>; 33 #size-cells = <2>; 37 compatible = "shared-dma-pool"; [all …]
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| D | mt7986a-rfb.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 7 /dts-v1/; 8 #include <dt-bindings/pinctrl/mt65xx.h> 14 chassis-type = "embedded"; 15 compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a"; 22 stdout-path = "serial0:115200n8"; 30 reg_1p8v: regulator-1p8v { 31 compatible = "regulator-fixed"; 32 regulator-name = "fixed-1.8V"; 33 regulator-min-microvolt = <1800000>; [all …]
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| D | mt8183-evb.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 8 /dts-v1/; 14 chassis-type = "embedded"; 15 compatible = "mediatek,mt8183-evb", "mediatek,mt8183"; 27 stdout-path = "serial0:921600n8"; 30 reserved-memory { 31 #address-cells = <2>; 32 #size-cells = <2>; 35 compatible = "shared-dma-pool"; 37 no-map; [all …]
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| D | mt8365-evk.dts | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2021-2022 BayLibre, SAS. 9 /dts-v1/; 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/input/input.h> 13 #include <dt-bindings/pinctrl/mt8365-pinfunc.h> 19 compatible = "mediatek,mt8365-evk", "mediatek,mt8365"; 26 stdout-path = "serial0:921600n8"; 31 compatible = "linaro,optee-tz"; 36 gpio-keys { [all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/rockchip/ |
| D | rk3588-edgeble-neu6a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 compatible = "edgeble,neural-compute-module-6a", "rockchip,rk3588"; 13 vcc12v_dcin: vcc12v-dcin-regulator { 14 compatible = "regulator-fixed"; 15 regulator-name = "vcc12v_dcin"; 16 regulator-always-on; 17 regulator-boot-on; 18 regulator-min-microvolt = <12000000>; 19 regulator-max-microvolt = <12000000>; 24 bus-width = <8>; [all …]
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| D | rk3588s-khadas-edge2.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 /dts-v1/; 5 #include <dt-bindings/gpio/gpio.h> 6 #include <dt-bindings/pinctrl/rockchip.h> 19 stdout-path = "serial2:1500000n8"; 24 bus-width = <8>; 25 no-sdio; 26 no-sd; 27 non-removable; 28 mmc-hs400-1_8v; [all …]
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| /kernel/linux/linux-6.6/drivers/mmc/core/ |
| D | host.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * linux/drivers/mmc/core/host.c 6 * Copyright (C) 2007-2008 Pierre Ossman 9 * MMC host class device management 23 #include <linux/mmc/host.h> 24 #include <linux/mmc/card.h> 25 #include <linux/mmc/slot-gpio.h> 30 #include "slot-gpio.h" 47 if (!host->bus_ops) in mmc_host_class_prepare() 51 if (host->bus_ops->pre_suspend) in mmc_host_class_prepare() [all …]
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| /kernel/linux/linux-6.6/include/linux/mmc/ |
| D | host.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 3 * linux/include/linux/mmc/host.h 12 #include <linux/fault-inject.h> 14 #include <linux/mmc/core.h> 15 #include <linux/mmc/card.h> 16 #include <linux/mmc/pm.h> 17 #include <linux/dma-direction.h> 18 #include <linux/blk-crypto-profile.h> 141 * ios->clock might be 0. For some controllers, setting 0Hz 151 * 1 for a read-only card [all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/sprd/ |
| D | whale2.dtsi | 6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 9 #include <dt-bindings/clock/sprd,sc9860-clk.h> 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 17 compatible = "simple-bus"; 18 #address-cells = <2>; 19 #size-cells = <2>; 67 ap-apb { 68 compatible = "simple-bus"; [all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/sprd/ |
| D | whale2.dtsi | 6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 9 #include <dt-bindings/clock/sprd,sc9860-clk.h> 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 17 compatible = "simple-bus"; 18 #address-cells = <2>; 19 #size-cells = <2>; 67 ap-apb { 68 compatible = "simple-bus"; [all …]
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| /kernel/linux/linux-5.10/include/linux/mmc/ |
| D | host.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 3 * linux/include/linux/mmc/host.h 12 #include <linux/fault-inject.h> 14 #include <linux/mmc/core.h> 15 #include <linux/mmc/card.h> 16 #include <linux/mmc/pm.h> 17 #include <linux/dma-direction.h> 108 * ios->clock might be 0. For some controllers, setting 0Hz 118 * 1 for a read-only card 119 * -ENOSYS when not supported (equal to NULL callback) [all …]
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| /kernel/linux/linux-5.10/drivers/mmc/core/ |
| D | host.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * linux/drivers/mmc/core/host.c 6 * Copyright (C) 2007-2008 Pierre Ossman 9 * MMC host class device management 23 #include <linux/mmc/host.h> 24 #include <linux/mmc/card.h> 25 #include <linux/mmc/slot-gpio.h> 29 #include "slot-gpio.h" 46 if (!host->bus_ops) in mmc_host_class_prepare() 50 if (host->bus_ops->pre_suspend) in mmc_host_class_prepare() [all …]
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| /kernel/linux/linux-5.10/drivers/mmc/host/ |
| D | sdhci-msm.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver 5 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. 11 #include <linux/mmc/mmc.h> 21 #include "sdhci-pltfm.h" 120 #define INVALID_TUNING_PHASE -1 134 /* Max load for eMMC Vdd-io supply */ 138 msm_host->var_ops->msm_readl_relaxed(host, offset) 141 msm_host->var_ops->msm_writel_relaxed(val, host, offset) 265 struct mmc_host *mmc; member [all …]
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| D | dw_mmc-exynos.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 11 #include <linux/mmc/host.h> 12 #include <linux/mmc/mmc.h> 19 #include "dw_mmc-pltfm.h" 20 #include "dw_mmc-exynos.h" 22 /* Variations in Exynos specific dw-mshc controller */ 52 .compatible = "samsung,exynos4210-dw-mshc", 55 .compatible = "samsung,exynos4412-dw-mshc", 58 .compatible = "samsung,exynos5250-dw-mshc", 61 .compatible = "samsung,exynos5420-dw-mshc", [all …]
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| D | renesas_sdhi_core.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2015-19 Renesas Electronics Corporation 6 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang 7 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 13 * Copyright 2004-2005 Phil Blundell 14 * Copyright 2007-2008 OpenedHand Ltd. 28 #include <linux/mmc/host.h> 29 #include <linux/mmc/mmc.h> 30 #include <linux/mmc/slot-gpio.h> 35 #include <linux/pinctrl/pinctrl-state.h> [all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/mediatek/ |
| D | mt8183-evb.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 8 /dts-v1/; 14 compatible = "mediatek,mt8183-evb", "mediatek,mt8183"; 26 stdout-path = "serial0:921600n8"; 29 reserved-memory { 30 #address-cells = <2>; 31 #size-cells = <2>; 34 compatible = "shared-dma-pool"; 36 no-map; 46 pinctrl-names = "default"; [all …]
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| /kernel/linux/linux-6.6/drivers/mmc/host/ |
| D | sdhci-msm.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver 5 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. 10 #include <linux/mmc/mmc.h> 23 #include "sdhci-cqhci.h" 24 #include "sdhci-pltfm.h" 123 #define INVALID_TUNING_PHASE -1 140 /* Max load for eMMC Vdd-io supply */ 146 /* Max load for SD Vdd-io supply */ 150 msm_host->var_ops->msm_readl_relaxed(host, offset) [all …]
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| D | renesas_sdhi_core.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2015-19 Renesas Electronics Corporation 6 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang 7 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 13 * Copyright 2004-2005 Phil Blundell 14 * Copyright 2007-2008 OpenedHand Ltd. 26 #include <linux/mmc/host.h> 27 #include <linux/mmc/mmc.h> 28 #include <linux/mmc/slot-gpio.h> 31 #include <linux/pinctrl/pinctrl-state.h> [all …]
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