| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | pmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - arm,armv8-pmuv3 # Only for s/w models
24 - arm,arm1136-pmu
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/ |
| D | pmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - apple,avalanche-pmu
24 - apple,blizzard-pmu
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/timer/ |
| D | arm,arch_timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
24 - items:
25 - const: arm,cortex-a15-timer
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/ |
| D | arm,arch_timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
24 - items:
25 - enum:
[all …]
|
| /kernel/uniproton/ |
| D | uniproton.gni | 1 # Copyright (c) 2022-2022 Huawei Technologies Co., Ltd. All rights reserved.
8 # EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
11 # Create: 2022-09-21
27 " --header-path $MENUCONFIG_H" + " --file-list kconfig_files.txt" +
28 " --env-list kconfig_env.txt" + " --config-out config.gni" ],
42 cmd = "grep -c '^\s*\(kernel_module\|hdf_driver\)\s*(\s*\S*\s*)\s*{\s*\$' $build_gn"
48 …cmd = "if grep -q '^\s*\(config\s*(\s*\"public\"\s*)\|module_group\s*(\s*\"\S*\"\s*)\)\s*{\s*\$' $…
59 …cmd = "if grep -q '^\s*\(module_group\|group\)\s*(\s*\"$current_dir_name\"\s*)\s*{\s*\$' $build_gn…
233 KERNEL_LWIP_INCLUDE_DIRS = [ "$OSTOPDIR/net/lwip-2.1/include" ]
236 "$OSTOPDIR/net/lwip-2.1/src/driverif.c",
[all …]
|
| /kernel/linux/linux-5.10/Documentation/arm/ |
| D | marvel.rst | 13 ------------
16 - 88F5082
17 - 88F5181
18 - 88F5181L
19 - 88F5182
21 … - Datasheet: http://www.embeddedarm.com/documentation/third-party/MV88F5182-datasheet.pdf
22 …- Programmer's User Guide: http://www.embeddedarm.com/documentation/third-party/MV88F5182-opensour…
23 … - User Manual: http://www.embeddedarm.com/documentation/third-party/MV88F5182-usermanual.pdf
24 - 88F5281
26 …- Datasheet: http://www.ocmodshop.com/images/reviews/networking/qnap_ts409u/marvel_88f5281_data_sh…
[all …]
|
| D | kernel_mode_neon.rst | 6 -------------
10 '-march=armv7-a -mfpu=neon -mfloat-abi=softfp'
18 ------------
25 non-preemptible section for reasons outlined below.
29 -------------------------
50 ----------------------------
67 --------------------
69 like IEEE-754 compliant underflow handling etc. When the VFP unit needs such
80 ---------------------------------------
84 instructions of its own at -O3 level if -mfpu=neon is selected, and even if the
[all …]
|
| /kernel/liteos_a/arch/arm/arm/src/include/ |
| D | armv7_pmu_pri.h | 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
53 #define ARMV7_PMNC_DP (1U << 5) /* Disable CCNT if non-invasive debug */
59 /* armv7 counters index */
65 #define ARMV7_IDX_COUNTER_LAST (ARMV7_IDX_CYCLE_COUNTER + ARMV7_MAX_COUNTERS - 1)
66 #define ARMV7_COUNTER_MASK (ARMV7_MAX_COUNTERS - 1)
68 /* armv7 event counter index mapping */
70 #define ARMV7_IDX2CNT(x) (((x) - ARMV7_IDX_COUNTER0) & ARMV7_COUNTER_MASK)
76 ARMV7_PERF_HW_DCACHE_MISSES = 0x03, /* dcache-misses */
78 ARMV7_PERF_HW_ICACHE_MISSES = 0x01, /* icache-misses */
[all …]
|
| /kernel/linux/linux-6.6/arch/arm/mm/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
17 A 32-bit RISC microprocessor based on the ARM7 processor core
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
69 A 32-bit RISC microprocessor based on the ARM9 processor core
182 ARM940T is a member of the ARM9TDMI family of general-
184 instruction and 4KB data cases, each with a 4-word line
190 # ARM946E-S
201 ARM946E-S is a member of the ARM9E-S family of high-
202 performance, 32-bit system-on-chip processor solutions.
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/mm/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
17 A 32-bit RISC microprocessor based on the ARM7 processor core
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
69 A 32-bit RISC microprocessor based on the ARM9 processor core
182 ARM940T is a member of the ARM9TDMI family of general-
184 instruction and 4KB data cases, each with a 4-word line
190 # ARM946E-S
201 ARM946E-S is a member of the ARM9E-S family of high-
202 performance, 32-bit system-on-chip processor solutions.
[all …]
|
| /kernel/linux/linux-6.6/Documentation/trace/coresight/ |
| D | coresight-cpu-debug.rst | 9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
13 debug module and it is mainly used for two modes: self-hosted debug and
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
29 --------------
31 - During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
32 registers to decide if sample-based profiling is implemented or not. On some
36 - At the time this documentation was written, the debug driver mainly relies on
[all …]
|
| /kernel/linux/linux-5.10/Documentation/trace/coresight/ |
| D | coresight-cpu-debug.rst | 9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
13 debug module and it is mainly used for two modes: self-hosted debug and
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
29 --------------
31 - During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
32 registers to decide if sample-based profiling is implemented or not. On some
36 - At the time this documentation was written, the debug driver mainly relies on
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/include/asm/ |
| D | cacheflush.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1999-2002 Russell King
12 #include <asm/glue-cache.h>
17 #define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
29 * The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
35 * See Documentation/core-api/cachetlb.rst for more information.
37 * effects are cache-type (VIVT/VIPT/PIPT) specific.
42 * Currently only needed for cache-v6.S and cache-v7.S, see
52 * inner shareable and invalidate the I-cache.
65 * - start - user start address (inclusive, page aligned)
[all …]
|
| /kernel/linux/linux-6.6/arch/arm/include/asm/ |
| D | cacheflush.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1999-2002 Russell King
12 #include <asm/glue-cache.h>
17 #define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
29 * The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
35 * See Documentation/core-api/cachetlb.rst for more information.
37 * effects are cache-type (VIVT/VIPT/PIPT) specific.
42 * Currently only needed for cache-v6.S and cache-v7.S, see
52 * inner shareable and invalidate the I-cache.
65 * - start - user start address (inclusive, page aligned)
[all …]
|
| /kernel/linux/linux-6.6/Documentation/arch/arm/ |
| D | marvell.rst | 13 ------------
16 - 88F5082
17 - 88F5181 a.k.a Orion-1
18 - 88F5181L a.k.a Orion-VoIP
19 - 88F5182 a.k.a Orion-NAS
21 …- Datasheet: https://web.archive.org/web/20210124231420/http://csclub.uwaterloo.ca/~board/ts7800/M…
22 …- Programmer's User Guide: https://web.archive.org/web/20210124231536/http://csclub.uwaterloo.ca/~…
23 …- User Manual: https://web.archive.org/web/20210124231631/http://csclub.uwaterloo.ca/~board/ts7800…
24 …- Functional Errata: https://web.archive.org/web/20210704165540/https://www.digriz.org.uk/ts78xx/8…
25 - 88F5281 a.k.a Orion-2
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/common/ |
| D | secure_cntvoff.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
13 .arch armv7-a
15 * CNTVOFF has to be initialized either from non-secure Hypervisor
23 mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */
|
| /kernel/linux/linux-6.6/arch/arm/common/ |
| D | secure_cntvoff.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
13 .arch armv7-a
15 * CNTVOFF has to be initialized either from non-secure Hypervisor
23 mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */
|
| /kernel/uniproton/src/arch/include/ |
| D | prt_attr_external.h | 2 * Copyright (c) 2009-2022 Huawei Technologies Co., Ltd. All rights reserved.
9 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12 * Create: 2009-12-22
21 #include "../cpu/armv7-m/common/os_attr_armv7_m_external.h"
|
| D | prt_cpu_external.h | 2 * Copyright (c) 2009-2022 Huawei Technologies Co., Ltd. All rights reserved.
9 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12 * Create: 2009-10-05
35 #include "../cpu/armv7-m/common/os_cpu_armv7_m_external.h"
|
| /kernel/linux/linux-5.10/tools/perf/util/ |
| D | cs-etm.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
21 /* PMU->type (32 bit), total # of CPUs (32 bit) */
61 * table 7-12 Encoding of Exception[3:0] for non-ARMv7-M processors.
83 * table 6-12 Possible values for the TYPE field in an Exception instruction
84 * trace packet, for ARMv7-A/R and ARMv8-A/R PEs.
139 * When working with per-thread scenarios the process under trace can
188 return -1; in cs_etm__process_auxtrace_info()
194 return -1; in cs_etm__get_cpu()
202 return -1; in cs_etm__etmq_set_tid()
|
| /kernel/linux/linux-5.10/drivers/iommu/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
2 # The IOVA library may also be used by non-IOMMU_API users
6 # The IOASID library may also be used by non-IOMMU_API users
33 bool "ARMv7/v8 Long Descriptor Format"
39 sizes at both stage-1 and stage-2, as well as address spaces
40 up to 48-bits in size.
46 Enable self-tests for LPAE page table allocator. This performs
47 a series of page-table consistency checks during boot.
52 bool "ARMv7/v8 Short Descriptor Format"
56 Enable support for the ARM Short-descriptor pagetable format.
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,tegra194-cbb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sumit Gupta <sumitg@nvidia.com>
15 multiple hierarchical sub-NOCs (Network-on-Chip) and connects various
20 "AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC"
28 - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the
31 - For other initiators, the ERD is disabled. So, the access issuing
34 include all engines using Cortex-R5 (which is ARMv7 CPU cluster) and
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/mach-omap2/ |
| D | omap-headsmp.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2009-2014 Texas Instruments, Inc.
58 .arch armv7-a
113 * bit 1 == Non-Secure Enable
114 * The Non-Secure banked register has not changed
116 * GIC restoration will cause a problem to CPU0 Non-Secure SW.
120 * 2) CPU1 must re-enable the GIC distributor on
|
| /kernel/linux/linux-6.6/arch/arm/mach-omap2/ |
| D | omap-headsmp.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2009-2014 Texas Instruments, Inc.
58 .arch armv7-a
113 * bit 1 == Non-Secure Enable
114 * The Non-Secure banked register has not changed
116 * GIC restoration will cause a problem to CPU0 Non-Secure SW.
120 * 2) CPU1 must re-enable the GIC distributor on
|
| /kernel/linux/linux-6.6/arch/arm64/kernel/ |
| D | compat_alignment.c | 1 // SPDX-License-Identifier: GPL-2.0-only
16 * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998
29 #define LDSTHD_I_BIT(i) (i & (1 << 22)) /* double/half-word immed */
39 /* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */
58 offset.un = -offset.un; in do_alignment_finish_ldst()
64 regs->regs[RN_BITS(instr)] = addr; in do_alignment_finish_ldst()
75 /* ARMv7 Thumb-2 32-bit LDRD/STRD */ in do_alignment_ldrdstrd()
91 regs->regs[rd] = val; in do_alignment_ldrdstrd()
92 regs->regs[rd2] = val2; in do_alignment_ldrdstrd()
94 if (put_user(regs->regs[rd], (u32 __user *)addr) || in do_alignment_ldrdstrd()
[all …]
|