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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/
Dcoresight.txt1 * CoreSight Components:
3 CoreSight components are compliant with the ARM CoreSight architecture
8 sink. Each CoreSight component device should use these properties to describe
11 * Required properties for all components *except* non-configurable replicators
12 and non-configurable funnels:
16 - Embedded Trace Buffer (version 1.0):
17 "arm,coresight-etb10", "arm,primecell";
19 - Trace Port Interface Unit:
20 "arm,coresight-tpiu", "arm,primecell";
22 - Trace Memory Controller, used for Embedded Trace Buffer(ETB),
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Dcoresight-cti.yaml1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/coresight-cti.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: ARM Coresight Cross Trigger Interface (CTI) device.
11 The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected
12 to one or more CoreSight components and/or a CPU, with CTIs interconnected in
15 not part of the CoreSight graph described in the general CoreSight bindings
16 file coresight.txt.
38 indicate this feature (arm,coresight-cti-v8-arch).
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/
Darm,coresight-cti.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: ARM Coresight Cross Trigger Interface (CTI) device.
11 The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected
12 to one or more CoreSight components and/or a CPU, with CTIs interconnected in
15 not part of the CoreSight graph.
37 indicate this feature (arm,coresight-cti-v8-arch).
48 between CTI and other CoreSight components.
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Darm,coresight-static-funnel.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-static-funnel.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm CoreSight Static Trace Bus Funnel
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
16 CoreSight components are compliant with the ARM CoreSight architecture
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Darm,coresight-static-replicator.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-static-replicator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm CoreSight Static Trace Bus Replicator
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
16 CoreSight components are compliant with the ARM CoreSight architecture
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Darm,coresight-catu.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-catu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm Coresight Address Translation Unit (CATU)
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
16 CoreSight components are compliant with the ARM CoreSight architecture
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/kernel/linux/linux-5.10/drivers/hwtracing/coresight/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Coresight configuration
5 menuconfig CORESIGHT config
6 tristate "CoreSight Tracing Support"
12 This framework provides a kernel interface for the CoreSight debug
14 a topological view of the CoreSight components based on a DT
19 module will be called coresight.
21 if CORESIGHT
23 tristate "CoreSight Link and Sink drivers"
25 This enables support for CoreSight link and sink drivers that are
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Dcoresight-platform.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/coresight.h>
21 #include "coresight-priv.h"
29 if (pdata->nr_outport) { in coresight_alloc_conns()
30 pdata->conns = devm_kcalloc(dev, pdata->nr_outport, in coresight_alloc_conns()
31 sizeof(*pdata->conns), GFP_KERNEL); in coresight_alloc_conns()
32 if (!pdata->conns) in coresight_alloc_conns()
33 return -ENOMEM; in coresight_alloc_conns()
45 * If we have a non-configurable replicator, it will be found on the in coresight_find_device_by_fwnode()
53 * We have a configurable component - circle through the AMBA bus in coresight_find_device_by_fwnode()
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Dcoresight-cti-platform.c1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/coresight.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
14 #include "coresight-cti.h"
15 #include "coresight-priv.h"
23 #define CTI_DT_CONNS "trig-conns"
26 #define CTI_DT_V8ARCH_COMPAT "arm,coresight-cti-v8-arch"
27 #define CTI_DT_CSDEV_ASSOC "arm,cs-dev-assoc"
28 #define CTI_DT_TRIGIN_SIGS "arm,trig-in-sigs"
29 #define CTI_DT_TRIGOUT_SIGS "arm,trig-out-sigs"
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/kernel/linux/linux-6.6/arch/arm/boot/dts/hisilicon/
Dhip04.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-2014 HiSilicon Ltd.
6 * Copyright (C) 2013-2014 Linaro Ltd.
12 /* memory bus is 64-bit */
13 #address-cells = <2>;
14 #size-cells = <2>;
21 compatible = "hisilicon,hip04-bootwrapper";
22 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
26 #address-cells = <1>;
27 #size-cells = <0>;
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dhip04.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-2014 Hisilicon Ltd.
6 * Copyright (C) 2013-2014 Linaro Ltd.
12 /* memory bus is 64-bit */
13 #address-cells = <2>;
14 #size-cells = <2>;
21 compatible = "hisilicon,hip04-bootwrapper";
22 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
26 #address-cells = <1>;
27 #size-cells = <0>;
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/kernel/linux/linux-6.6/Documentation/trace/coresight/
Dcoresight-cpu-debug.rst2 Coresight CPU Debug Module
9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
13 debug module and it is mainly used for two modes: self-hosted debug and
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
29 --------------
31 - During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
32 registers to decide if sample-based profiling is implemented or not. On some
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Dcoresight-ect.rst1 .. SPDX-License-Identifier: GPL-2.0
4 CoreSight Embedded Cross Trigger (CTI & CTM).
11 --------------------
13 The CoreSight Cross Trigger Interface (CTI) is a hardware device that takes
21 0 C 0----------->: : +======>(other CTI channel IO)
22 0 P 0<-----------: : v
24 0000000 : CTI :<=========>*CTM*<====>: CTI :---+
25 ####### in_trigs : : (id 0-3) ***** ::::::: v
26 # ETM #----------->: : ^ #######
27 # #<-----------: : +---# ETR #
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Dcoresight.rst2 Coresight - HW Assisted Tracing on ARM
9 ------------
11 Coresight is an umbrella of technologies allowing for the debugging of ARM
24 flows through the coresight system (via ATB bus) using links that are connecting
25 the emanating source to a sink(s). Sinks serve as endpoints to the coresight
28 host without fear of filling up the onboard coresight memory buffer.
30 At typical coresight system would look like this::
38 0 CPU 0<-->: C : 0 CPU 0<-->: C : : C : @ STM @ || System ||
39 |->0000000 : T : |->0000000 : T : : T :<--->@@@@@ || Memory ||
40 | #######<-->: I : | #######<-->: I : : I : @@@<-| ||||||||||||
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/kernel/linux/linux-5.10/Documentation/trace/coresight/
Dcoresight-cpu-debug.rst2 Coresight CPU Debug Module
9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
13 debug module and it is mainly used for two modes: self-hosted debug and
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
29 --------------
31 - During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
32 registers to decide if sample-based profiling is implemented or not. On some
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Dcoresight-ect.rst1 .. SPDX-License-Identifier: GPL-2.0
4 CoreSight Embedded Cross Trigger (CTI & CTM).
11 --------------------
13 The CoreSight Cross Trigger Interface (CTI) is a hardware device that takes
21 0 C 0----------->: : +======>(other CTI channel IO)
22 0 P 0<-----------: : v
24 0000000 : CTI :<=========>*CTM*<====>: CTI :---+
25 ####### in_trigs : : (id 0-3) ***** ::::::: v
26 # ETM #----------->: : ^ #######
27 # #<-----------: : +---# ETR #
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Dcoresight.rst2 Coresight - HW Assisted Tracing on ARM
9 ------------
11 Coresight is an umbrella of technologies allowing for the debugging of ARM
24 flows through the coresight system (via ATB bus) using links that are connecting
25 the emanating source to a sink(s). Sinks serve as endpoints to the coresight
28 host without fear of filling up the onboard coresight memory buffer.
30 At typical coresight system would look like this::
38 0 CPU 0<-->: C : 0 CPU 0<-->: C : : C : @ STM @ || System ||
39 |->0000000 : T : |->0000000 : T : : T :<--->@@@@@ || Memory ||
40 | #######<-->: I : | #######<-->: I : : I : @@@<-| ||||||||||||
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/kernel/linux/linux-6.6/drivers/hwtracing/coresight/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Coresight configuration
5 menuconfig CORESIGHT config
6 tristate "CoreSight Tracing Support"
13 This framework provides a kernel interface for the CoreSight debug
15 a topological view of the CoreSight components based on a DT
20 module will be called coresight.
22 if CORESIGHT
24 tristate "CoreSight Link and Sink drivers"
26 This enables support for CoreSight link and sink drivers that are
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Dcoresight-platform.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/coresight.h>
19 #include "coresight-priv.h"
24 * If the output port is already assigned on this device, return -EINVAL
37 for (i = 0; i < pdata->nr_outconns; ++i) { in coresight_add_out_conn()
38 conn = pdata->out_conns[i]; in coresight_add_out_conn()
39 /* Output == -1 means ignore the port for example for helpers */ in coresight_add_out_conn()
40 if (conn->src_port != -1 && in coresight_add_out_conn()
41 conn->src_port == new_conn->src_port) { in coresight_add_out_conn()
43 conn->src_port); in coresight_add_out_conn()
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Dcoresight-cti-platform.c1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/coresight.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
14 #include "coresight-cti.h"
15 #include "coresight-priv.h"
23 #define CTI_DT_CONNS "trig-conns"
26 #define CTI_DT_V8ARCH_COMPAT "arm,coresight-cti-v8-arch"
27 #define CTI_DT_CSDEV_ASSOC "arm,cs-dev-assoc"
28 #define CTI_DT_TRIGIN_SIGS "arm,trig-in-sigs"
29 #define CTI_DT_TRIGOUT_SIGS "arm,trig-out-sigs"
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/kernel/linux/linux-6.6/Documentation/ABI/testing/
Dsysfs-bus-coresight-devices-etm4x1 What: /sys/bus/coresight/devices/etm<N>/enable_source
8 of coresight components linking the source to the sink is
9 configured and managed automatically by the coresight framework.
11 What: /sys/bus/coresight/devices/etm<N>/cpu
17 What: /sys/bus/coresight/devices/etm<N>/nr_pe_cmp
24 What: /sys/bus/coresight/devices/etm<N>/nr_addr_cmp
31 What: /sys/bus/coresight/devices/etm<N>/nr_cntr
38 What: /sys/bus/coresight/devices/etm<N>/nr_ext_inp
44 What: /sys/bus/coresight/devices/etm<N>/numcidc
51 What: /sys/bus/coresight/devices/etm<N>/numvmidc
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/kernel/linux/linux-5.10/Documentation/ABI/testing/
Dsysfs-bus-coresight-devices-etm4x1 What: /sys/bus/coresight/devices/etm<N>/enable_source
8 of coresight components linking the source to the sink is
9 configured and managed automatically by the coresight framework.
11 What: /sys/bus/coresight/devices/etm<N>/cpu
17 What: /sys/bus/coresight/devices/etm<N>/nr_pe_cmp
24 What: /sys/bus/coresight/devices/etm<N>/nr_addr_cmp
31 What: /sys/bus/coresight/devices/etm<N>/nr_cntr
38 What: /sys/bus/coresight/devices/etm<N>/nr_ext_inp
44 What: /sys/bus/coresight/devices/etm<N>/numcidc
51 What: /sys/bus/coresight/devices/etm<N>/numvmidc
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/kernel/linux/linux-6.6/arch/arm64/boot/dts/sprd/
Dsc9863a.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/clock/sprd,sc9863a-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #address-cells = <2>;
15 #size-cells = <0>;
17 cpu-map {
48 compatible = "arm,cortex-a55";
50 enable-method = "psci";
51 cpu-idle-states = <&CORE_PD>;
56 compatible = "arm,cortex-a55";
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/sprd/
Dsc9863a.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/clock/sprd,sc9863a-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #address-cells = <2>;
15 #size-cells = <0>;
17 cpu-map {
48 compatible = "arm,cortex-a55";
50 enable-method = "psci";
51 cpu-idle-states = <&CORE_PD>;
56 compatible = "arm,cortex-a55";
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/kernel/linux/linux-6.6/tools/perf/util/
Dcs-etm.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 /* PMU->type (32 bit), total # of CPUs (32 bit) */
40 * CoreSight Trace ID. ...TRACEIDR metadata will be set to legacy values
65 /* define fixed version 0 length - allow new format reader to read old files. */
66 #define CS_ETM_NR_TRC_PARAMS_V0 (CS_ETM_ETMIDR - CS_ETM_ETMCR + 1)
83 /* define fixed version 0 length - allow new format reader to read old files. */
84 #define CS_ETMV4_NR_TRC_PARAMS_V0 (CS_ETMV4_TRCAUTHSTATUS - CS_ETMV4_TRCCONFIGR + 1)
106 * Check for valid CoreSight trace ID. If an invalid value is present in the metadata,
114 * table 7-12 Encoding of Exception[3:0] for non-ARMv7-M processors.
136 * table 6-12 Possible values for the TYPE field in an Exception instruction
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