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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dbaikal,bt1-ccu-pll.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
23 2) PLLs clocks generators (PLLs) - described in this binding file.
[all …]
Dbaikal,bt1-ccu-div.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit Dividers
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
22 registers. Baikal-T1 CCU is logically divided into the next components:
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dbaikal,bt1-ccu-pll.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
23 2) PLLs clocks generators (PLLs) - described in this binding file.
[all …]
Dbaikal,bt1-ccu-div.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit Dividers
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
22 registers. Baikal-T1 CCU is logically divided into the next components:
[all …]
/kernel/linux/linux-6.6/drivers/thermal/ti-soc-thermal/
Dti-bandgap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
26 * +----------+----------------+
28 * +---------------------------+
32 * +-------------------+ +-----------------+
33 * | struct ti_bandgap |-->| struct device * |
34 * +----------+--------+ +-----------------+
38 * +------------------------+
40 * +------------------------+
44 * +------------+------------------------------------------------------+
[all …]
/kernel/linux/linux-5.10/drivers/thermal/ti-soc-thermal/
Dti-bandgap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
26 * +----------+----------------+
28 * +---------------------------+
32 * +-------------------+ +-----------------+
33 * | struct ti_bandgap |-->| struct device * |
34 * +----------+--------+ +-----------------+
38 * +------------------------+
40 * +------------------------+
44 * +------------+------------------------------------------------------+
[all …]
/kernel/linux/linux-6.6/scripts/
Dspelling.txt728 gatable||gateable
1047 none existent||non-existent
1681 vicefersa||vice-versa
/kernel/linux/linux-6.6/drivers/mtd/nand/raw/brcmnand/
Dbrcmnand.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2010-2015 Broadcom Corporation
17 #include <linux/dma-mapping.h>
227 /* Some SoCs have a gateable clock for the controller */
237 /* List of NAND hosts (one for each chip-select) */
240 /* EDU info, per-transaction */
261 /* in-memory cache of the FLASH_CACHE, used only for some commands */
267 const u8 *cs_offsets; /* within each chip-select */
278 /* for low-power standby/resume only */
298 /* use for low-power standby/resume only */
[all …]
/kernel/linux/linux-5.10/drivers/mtd/nand/raw/brcmnand/
Dbrcmnand.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2010-2015 Broadcom Corporation
16 #include <linux/dma-mapping.h>
226 /* Some SoCs have a gateable clock for the controller */
236 /* List of NAND hosts (one for each chip-select) */
239 /* EDU info, per-transaction */
257 /* in-memory cache of the FLASH_CACHE, used only for some commands */
263 const u8 *cs_offsets; /* within each chip-select */
274 /* for low-power standby/resume only */
294 /* use for low-power standby/resume only */
[all …]