Searched +full:num +full:- +full:rx +full:- +full:queues (Results 1 – 25 of 416) sorted by relevance
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mailbox/ |
| D | ti,omap-mailbox.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Suman Anna <s-anna@ti.com> 19 Each mailbox IP block/cluster has a certain number of h/w fifo queues and 26 interrupt configuration registers, and have a rx and tx interrupt source per 28 appropriate programming of the rx and tx interrupt sources on the appropriate 31 The number of h/w fifo queues and interrupt lines dictate the usable 34 h/w fifo queues and interrupt lines between different instances. The interrupt [all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mailbox/ |
| D | omap-mailbox.txt | 10 Each mailbox IP block/cluster has a certain number of h/w fifo queues and output 16 programmable through a set of interrupt configuration registers, and have a rx 18 is achieved through the appropriate programming of the rx and tx interrupt 21 The number of h/w fifo queues and interrupt lines dictate the usable registers. 23 instance. DRA7xx has multiple instances with different number of h/w fifo queues 25 routed to different processor sub-systems on DRA7xx as they are routed through 35 a SoC. The sub-mailboxes are represented as child nodes of this parent node. 38 -------------------- 39 - compatible: Should be one of the following, 40 "ti,omap2-mailbox" for OMAP2420, OMAP2430 SoCs [all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | fsl-fec.txt | 4 - compatible : Should be "fsl,<soc>-fec" 5 - reg : Address and length of the register set for the device 6 - interrupts : Should contain fec interrupt 7 - phy-mode : See ethernet.txt file in the same directory 10 - phy-supply : regulator that powers the Ethernet PHY. 11 - phy-handle : phandle to the PHY device connected to this device. 12 - fixed-link : Assume a fixed link. See fixed-link.txt in the same directory. 13 Use instead of phy-handle. 14 - fsl,num-tx-queues : The property is valid for enet-avb IP, which supports 15 hw multi queues. Should specify the tx queue number, otherwise set tx queue [all …]
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| D | brcm,systemport.txt | 4 - compatible: should be one of: 5 "brcm,systemport-v1.00" 6 "brcm,systemportlite-v1.00" or 8 - reg: address and length of the register set for the device. 9 - interrupts: interrupts for the device, first cell must be for the rx 10 interrupts, and the second cell should be for the transmit queues. An 11 optional third interrupt cell for Wake-on-LAN can be specified 12 - local-mac-address: Ethernet MAC address (48 bits) of this adapter 13 - phy-mode: Should be a string describing the PHY interface to the 15 - fixed-link: see Documentation/devicetree/bindings/net/fixed-link.txt for [all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/ |
| D | brcm,systemport.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Florian Fainelli <f.fainelli@gmail.com> 15 - brcm,systemport-v1.00 16 - brcm,systemportlite-v1.00 17 - brcm,systemport 25 - description: interrupt line for RX queues 26 - description: interrupt line for TX queues 27 - description: interrupt line for Wake-on-LAN [all …]
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| D | fsl,fec.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Shawn Guo <shawnguo@kernel.org> 11 - Wei Fang <wei.fang@nxp.com> 12 - NXP Linux Team <linux-imx@nxp.com> 15 - $ref: ethernet-controller.yaml# 20 - enum: 21 - fsl,imx25-fec 22 - fsl,imx27-fec [all …]
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| /kernel/linux/linux-6.6/Documentation/netlink/specs/ |
| D | rt_link.yaml | 1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 3 name: rt-link 4 protocol: netlink-raw 11 - 12 name: ifinfo-flags 15 - 17 - 19 - 21 - 23 - [all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/rockchip/ |
| D | rk3568.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 12 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; 16 clock-names = "sata", "pmalive", "rxoob"; 19 phy-names = "sata-phy"; 20 ports-implemented = <0x1>; 21 power-domains = <&power RK3568_PD_PIPE>; 26 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; 31 compatible = "rockchip,rk3568-qos", "syscon"; 36 compatible = "rockchip,rk3568-qos", "syscon"; 41 compatible = "rockchip,rk3568-qos", "syscon"; [all …]
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| D | rk3588.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 #include "rk3588-pinctrl.dtsi" 11 compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; 16 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 21 compatible = "rockchip,rk3588-i2s-tdm"; 25 clock-names = "mclk_tx", "mclk_rx", "hclk"; 26 assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; 27 assigned-clock-parents = <&cru PLL_AUPLL>; 29 dma-names = "tx"; 30 power-domains = <&power RK3588_PD_VO0>; [all …]
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| /kernel/linux/linux-5.10/drivers/net/ethernet/intel/ice/ |
| D | ice.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 19 #include <linux/dma-mapping.h> 84 #define ICE_RES_MISC_VEC_ID (ICE_RES_VALID_BIT - 1) 94 #define ICE_MAX_MTU (ICE_AQ_SET_MAC_FRAME_SIZE_MAX - ICE_ETH_PKT_HDR_PAD) 100 #define ICE_TX_DESC(R, i) (&(((struct ice_tx_desc *)((R)->desc))[i])) 101 #define ICE_RX_DESC(R, i) (&(((union ice_32b_rx_flex_desc *)((R)->desc))[i])) 102 #define ICE_TX_CTX_DESC(R, i) (&(((struct ice_tx_ctx_desc *)((R)->desc))[i])) 103 #define ICE_TX_FDIRDESC(R, i) (&(((struct ice_fltr_desc *)((R)->desc))[i])) 107 for ((i) = 0; (i) < (pf)->num_alloc_vsi; (i)++) 109 /* Macros for each Tx/Rx ring in a VSI */ [all …]
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| /kernel/linux/linux-5.10/drivers/net/ethernet/amazon/ena/ |
| D | ena_netdev.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved. 56 #define ENA_DEFAULT_RX_COPYBREAK (256 - NET_IP_ALIGN) 79 /* Refill Rx queue when number of required descriptors is above 85 /* Number of queues to check for missing queues per timer service */ 90 #define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1)) 92 #define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1)) 94 (((idx) + (n)) & ((ring_size) - 1)) 99 #define ENA_IO_RXQ_IDX_TO_COMBINED_IDX(q) (((q) - 1) / 2) 121 #define ENA_XDP_MAX_MTU (ENA_PAGE_SIZE - ETH_HLEN - ETH_FCS_LEN - \ [all …]
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| /kernel/linux/linux-6.6/drivers/crypto/caam/ |
| D | dpseci.h | 1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 3 * Copyright 2013-2016 Freescale Semiconductor Inc. 4 * Copyright 2017-2018 NXP 21 * Maximum number of Tx/Rx queues per DPSECI object 26 * All queues considered; see dpseci_set_rx_queue() 28 #define DPSECI_ALL_QUEUES (u8)(-1) 41 * struct dpseci_cfg - Structure representing DPSECI configuration 44 * @num_tx_queues: num of queues towards the SEC 45 * @num_rx_queues: num of queues back from the SEC 49 * valid priorities are configured with values 1-8; [all …]
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| /kernel/linux/linux-5.10/drivers/crypto/caam/ |
| D | dpseci.h | 1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 3 * Copyright 2013-2016 Freescale Semiconductor Inc. 4 * Copyright 2017-2018 NXP 21 * Maximum number of Tx/Rx queues per DPSECI object 26 * All queues considered; see dpseci_set_rx_queue() 28 #define DPSECI_ALL_QUEUES (u8)(-1) 41 * struct dpseci_cfg - Structure representing DPSECI configuration 44 * @num_tx_queues: num of queues towards the SEC 45 * @num_rx_queues: num of queues back from the SEC 49 * valid priorities are configured with values 1-8; [all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | artpec6.dtsi | 2 * Device Tree Source for the Axis ARTPEC-6 SoC 4 * This file is dual-licensed: you can use it either under the terms 43 #include <dt-bindings/interrupt-controller/arm-gic.h> 44 #include <dt-bindings/dma/nbpfaxi.h> 45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h> 48 #address-cells = <1>; 49 #size-cells = <1>; 51 interrupt-parent = <&intc>; 54 #address-cells = <1>; 55 #size-cells = <0>; [all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/axis/ |
| D | artpec6.dtsi | 2 * Device Tree Source for the Axis ARTPEC-6 SoC 4 * This file is dual-licensed: you can use it either under the terms 43 #include <dt-bindings/interrupt-controller/arm-gic.h> 44 #include <dt-bindings/dma/nbpfaxi.h> 45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h> 48 #address-cells = <1>; 49 #size-cells = <1>; 51 interrupt-parent = <&intc>; 54 #address-cells = <1>; 55 #size-cells = <0>; [all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/ |
| D | imx8-ss-conn.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright 2018-2019 NXP 7 #include <dt-bindings/clock/imx8-lpcg.h> 8 #include <dt-bindings/firmware/imx/rsrc.h> 11 compatible = "simple-bus"; 12 #address-cells = <1>; 13 #size-cells = <1>; 16 conn_axi_clk: clock-conn-axi { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; [all …]
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| /kernel/linux/linux-6.6/drivers/net/ethernet/amazon/ena/ |
| D | ena_netdev.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved. 60 #define ENA_DEFAULT_RX_COPYBREAK (256 - NET_IP_ALIGN) 77 /* Refill Rx queue when number of required descriptors is above 83 /* Number of queues to check for missing queues per timer service */ 88 #define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1)) 90 #define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1)) 92 (((idx) + (n)) & ((ring_size) - 1)) 97 #define ENA_IO_RXQ_IDX_TO_COMBINED_IDX(q) (((q) - 1) / 2) 134 /* num of ena desc for this specific skb [all …]
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| D | ena_xdp.c | 1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 3 * Copyright 2015-2021 Amazon.com, Inc. or its affiliates. All rights reserved. 12 tx_info = &tx_ring->tx_buffer_info[req_id]; in validate_xdp_req_id() 13 if (likely(tx_info->xdpf)) in validate_xdp_req_id() 24 struct ena_adapter *adapter = tx_ring->adapter; in ena_xdp_tx_map_frame() 31 tx_info->xdpf = xdpf; in ena_xdp_tx_map_frame() 32 data = tx_info->xdpf->data; in ena_xdp_tx_map_frame() 33 size = tx_info->xdpf->len; in ena_xdp_tx_map_frame() 35 if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { in ena_xdp_tx_map_frame() 37 push_len = min_t(u32, size, tx_ring->tx_max_header_size); in ena_xdp_tx_map_frame() [all …]
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| /kernel/linux/linux-6.6/drivers/net/ethernet/cavium/liquidio/ |
| D | octeon_config.h | 7 * Copyright (c) 2003-2016 Cavium, Inc. 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 25 /*--------------------------CONFIG VALUES------------------------*/ 121 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) 122 #define CFG_GET_IQ_MAX_Q(cfg) ((cfg)->iq.max_iqs) 123 #define CFG_GET_IQ_PENDING_LIST_SIZE(cfg) ((cfg)->iq.pending_list_size) 124 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) 125 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) 126 #define CFG_GET_IQ_DB_TIMEOUT(cfg) ((cfg)->iq.db_timeout) 128 #define CFG_GET_IQ_INTR_PKT(cfg) ((cfg)->iq.iq_intr_pkt) [all …]
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| /kernel/linux/linux-5.10/drivers/net/ethernet/cavium/liquidio/ |
| D | octeon_config.h | 7 * Copyright (c) 2003-2016 Cavium, Inc. 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 25 /*--------------------------CONFIG VALUES------------------------*/ 121 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) 122 #define CFG_GET_IQ_MAX_Q(cfg) ((cfg)->iq.max_iqs) 123 #define CFG_GET_IQ_PENDING_LIST_SIZE(cfg) ((cfg)->iq.pending_list_size) 124 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) 125 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) 126 #define CFG_GET_IQ_DB_TIMEOUT(cfg) ((cfg)->iq.db_timeout) 128 #define CFG_GET_IQ_INTR_PKT(cfg) ((cfg)->iq.iq_intr_pkt) [all …]
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| /kernel/linux/linux-6.6/drivers/net/ethernet/intel/i40e/ |
| D | i40e.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2013 - 2021 Intel Corporation. */ 26 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024) 35 (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1) 39 (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64) 70 (&(((union i40e_rx_desc *)((R)->desc))[i])) 72 (&(((struct i40e_tx_desc *)((R)->desc))[i])) 74 (&(((struct i40e_tx_context_desc *)((R)->desc))[i])) 76 (&(((struct i40e_filter_program_desc *)((R)->desc))[i])) 154 #define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2) [all …]
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| /kernel/linux/linux-5.10/drivers/net/ethernet/google/gve/ |
| D | gve.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) 4 * Copyright (C) 2015-2019 Google, Inc. 10 #include <linux/dma-mapping.h> 27 /* 1 for management, 1 for rx, 1 for tx */ 30 /* Numbers of gve tx/rx stats in stats report. */ 37 /* Numbers of NIC tx/rx stats in stats report. */ 48 /* The page info for a single slot in the RX data queue */ 75 /* An RX ring that contains a power-of-two sized desc and data ring. */ 80 u64 rbytes; /* free-running bytes received */ 81 u64 rpackets; /* free-running packets received */ [all …]
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| /kernel/linux/linux-5.10/include/xen/interface/io/ |
| D | netif.h | 4 * Unified network-device I/O interface for Xen guest OSes. 24 * Copyright (c) 2003-2004, Keir Fraser 54 * If the client sends notification for rx requests then it should specify 55 * feature 'feature-rx-notify' via xenbus. Otherwise the backend will assume 60 * "feature-split-event-channels" is introduced to separate guest TX 61 * and RX notification. Backend either doesn't support this feature or 65 * channels for TX and RX, advertise them to backend as 66 * "event-channel-tx" and "event-channel-rx" respectively. If frontend 67 * doesn't want to use this feature, it just writes "event-channel" 72 * Multiple transmit and receive queues: [all …]
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| /kernel/linux/linux-6.6/include/xen/interface/io/ |
| D | netif.h | 1 /* SPDX-License-Identifier: MIT */ 5 * Unified network-device I/O interface for Xen guest OSes. 7 * Copyright (c) 2003-2004, Keir Fraser 37 * If the client sends notification for rx requests then it should specify 38 * feature 'feature-rx-notify' via xenbus. Otherwise the backend will assume 43 * "feature-split-event-channels" is introduced to separate guest TX 44 * and RX notification. Backend either doesn't support this feature or 48 * channels for TX and RX, advertise them to backend as 49 * "event-channel-tx" and "event-channel-rx" respectively. If frontend 50 * doesn't want to use this feature, it just writes "event-channel" [all …]
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| /kernel/linux/linux-5.10/drivers/net/ethernet/intel/i40e/ |
| D | i40e.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 53 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024) 62 (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1) 66 (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64) 95 (&(((union i40e_rx_desc *)((R)->desc))[i])) 97 (&(((struct i40e_tx_desc *)((R)->desc))[i])) 99 (&(((struct i40e_tx_context_desc *)((R)->desc))[i])) 101 (&(((struct i40e_filter_program_desc *)((R)->desc))[i])) 178 #define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2) [all …]
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