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Searched +full:ocelot +full:- +full:icpu +full:- +full:intr (Results 1 – 9 of 9) sorted by relevance

/kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/
Dmscc,ocelot-icpu-intr.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microsemi Ocelot SoC ICPU Interrupt Controller
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - $ref: /schemas/interrupt-controller.yaml#
16 the Microsemi Ocelot interrupt controller that is part of the
17 ICPU. It is connected directly to the MIPS core interrupt
23 - enum:
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dmscc,ocelot-icpu-intr.txt1 Microsemi Ocelot SoC ICPU Interrupt Controller
5 - compatible : should be "mscc,ocelot-icpu-intr"
6 - reg : Specifies base physical address and size of the registers.
7 - interrupt-controller : Identifies the node as an interrupt controller
8 - #interrupt-cells : Specifies the number of cells needed to encode an
10 - interrupts : Specifies the CPU interrupt the controller is connected to.
14 intc: interrupt-controller@70000070 {
15 compatible = "mscc,ocelot-icpu-intr";
17 #interrupt-cells = <1>;
18 interrupt-controller;
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/kernel/linux/linux-6.6/drivers/irqchip/
Dirq-mscc-ocelot.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Microsemi Ocelot IRQ controller driver
15 #define ICPU_CFG_INTR_DST_INTR_IDENT(_p, x) ((_p)->reg_off_ident + 0x4 * (x))
16 #define ICPU_CFG_INTR_INTR_TRIGGER(_p, x) ((_p)->reg_off_trigger + 0x4 * (x))
80 struct irq_domain *d = data->domain; in ocelot_irq_unmask()
81 struct chip_props *p = d->host_data; in ocelot_irq_unmask()
83 unsigned int mask = data->mask; in ocelot_irq_unmask()
90 irq_reg_writel(gc, mask, p->reg_off_sticky); in ocelot_irq_unmask()
92 *ct->mask_cache &= ~mask; in ocelot_irq_unmask()
93 irq_reg_writel(gc, mask, p->reg_off_ena_set); in ocelot_irq_unmask()
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/kernel/linux/linux-5.10/drivers/irqchip/
Dirq-mscc-ocelot.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Microsemi Ocelot IRQ controller driver
28 unsigned int mask = data->mask; in ocelot_irq_unmask()
37 *ct->mask_cache &= ~mask; in ocelot_irq_unmask()
70 return -EINVAL; in ocelot_irq_init()
76 return -ENOMEM; in ocelot_irq_init()
80 "icpu", handle_level_irq, in ocelot_irq_init()
88 gc->reg_base = of_iomap(node, 0); in ocelot_irq_init()
89 if (!gc->reg_base) { in ocelot_irq_init()
91 ret = -ENOMEM; in ocelot_irq_init()
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/kernel/linux/linux-6.6/arch/mips/boot/dts/mscc/
Dluton.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #address-cells = <1>;
6 #size-cells = <1>;
10 #address-cells = <1>;
11 #size-cells = <0>;
25 cpuintc: interrupt-controller {
26 #address-cells = <0>;
27 #interrupt-cells = <1>;
28 interrupt-controller;
29 compatible = "mti,cpu-interrupt-controller";
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Djaguar2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #address-cells = <1>;
8 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
29 cpuintc: interrupt-controller {
30 #address-cells = <0>;
31 #interrupt-cells = <1>;
32 interrupt-controller;
33 compatible = "mti,cpu-interrupt-controller";
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Dserval.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
28 cpuintc: interrupt-controller {
29 #address-cells = <0>;
30 #interrupt-cells = <1>;
31 interrupt-controller;
32 compatible = "mti,cpu-interrupt-controller";
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Docelot.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #address-cells = <1>;
6 #size-cells = <1>;
7 compatible = "mscc,ocelot";
10 #address-cells = <1>;
11 #size-cells = <0>;
25 cpuintc: interrupt-controller {
26 #address-cells = <0>;
27 #interrupt-cells = <1>;
28 interrupt-controller;
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/kernel/linux/linux-5.10/arch/mips/boot/dts/mscc/
Docelot.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #address-cells = <1>;
6 #size-cells = <1>;
7 compatible = "mscc,ocelot";
10 #address-cells = <1>;
11 #size-cells = <0>;
25 cpuintc: interrupt-controller {
26 #address-cells = <0>;
27 #interrupt-cells = <1>;
28 interrupt-controller;
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