| /kernel/linux/linux-6.6/drivers/nvmem/ |
| D | rockchip-otp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip OTP Driver
6 * Author: Finley Xiao <finley.xiao@rock-chips.com>
15 #include <linux/nvmem-provider.h>
22 /* OTP Register Offsets */
35 /* OTP Register bits and masks */
41 #define OTPC_SBPI_DONE BIT(1)
64 #define RK3588_BURST_NUM 1
68 #define RK3588_RD_DONE BIT(1)
85 static int rockchip_otp_reset(struct rockchip_otp *otp) in rockchip_otp_reset() argument
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| D | lan9662-otpc.c | 1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/nvmem-provider.h>
18 #define OTP_OTP_FUNC_CMD_OTP_PROGRAM BIT(1)
27 #define OTP_OTP_STATUS_OTP_CPUMPEN BIT(1)
47 static int lan9662_otp_power(struct lan9662_otp *otp, bool up) in lan9662_otp_power() argument
49 void __iomem *pwrdn = OTP_OTP_PWR_DN(otp->base); in lan9662_otp_power()
53 if (lan9662_otp_wait_flag_clear(OTP_OTP_STATUS(otp->base), in lan9662_otp_power()
55 return -ETIMEDOUT; in lan9662_otp_power()
63 static int lan9662_otp_execute(struct lan9662_otp *otp) in lan9662_otp_execute() argument
65 if (lan9662_otp_wait_flag_clear(OTP_OTP_CMD_GO(otp->base), in lan9662_otp_execute()
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| D | sunplus-ocotp.c | 1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/nvmem-provider.h>
21 * OTP memory
48 #define OTP_LOAD_SECURE_DATA BIT(1)
49 #define OTP_LOAD_SECURE_DATA_MASK ~BIT(1)
78 static int sp_otp_read_real(struct sp_ocotp_priv *otp, int addr, char *value) in sp_otp_read_real() argument
94 writel(readl(otp->base[OTPRX] + OTP_STATUS) & OTP_READ_DONE_MASK & in sp_otp_read_real()
95 OTP_LOAD_SECURE_DONE_MASK, otp->base[OTPRX] + OTP_STATUS); in sp_otp_read_real()
96 writel(addr, otp->base[OTPRX] + OTP_READ_ADDRESS); in sp_otp_read_real()
97 writel(readl(otp->base[OTPRX] + OTP_CONTROL_2) | OTP_READ, in sp_otp_read_real()
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| D | mxs-ocotp.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale MXS On-Chip OTP driver
15 #include <linux/nvmem-provider.h>
36 static int mxs_ocotp_wait(struct mxs_ocotp *otp) in mxs_ocotp_wait() argument
41 while (timeout--) { in mxs_ocotp_wait()
42 status = readl(otp->base); in mxs_ocotp_wait()
51 return -EBUSY; in mxs_ocotp_wait()
53 return -EIO; in mxs_ocotp_wait()
61 struct mxs_ocotp *otp = context; in mxs_ocotp_read() local
65 ret = clk_enable(otp->clk); in mxs_ocotp_read()
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| D | lpc18xx_otp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * NXP LPC18xx/43xx OTP memory NVMEM driver
10 * TODO: add support for writing OTP register via API in boot ROM.
15 #include <linux/nvmem-provider.h>
21 * LPC18xx OTP memory contains 4 banks with 4 32-bit words. Bank 0 starts
26 * Bank 1/2 is generale purpose or AES key storage for secure devices.
43 struct lpc18xx_otp *otp = context; in lpc18xx_otp_read() local
49 if (count > (LPC18XX_OTP_SIZE - index)) in lpc18xx_otp_read()
50 count = LPC18XX_OTP_SIZE - index; in lpc18xx_otp_read()
53 *buf++ = readl(otp->base + i * LPC18XX_OTP_WORD_SIZE); in lpc18xx_otp_read()
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
37 calibration data required for the PCIe or the USB-C PHY.
40 be called nvmem-apple-efuses.
43 tristate "Broadcom On-Chip OTP Controller support"
48 Say y here to enable read/write access to the Broadcom OTP
52 will be called nvmem-bcm-ocotp.
72 will be called nvmem-imx-iim.
75 tristate "i.MX 6/7/8 On-Chip OTP Controller support"
79 This is a driver for the On-Chip OTP Controller (OCOTP) available on
80 i.MX6 SoCs, providing access to 4 Kbits of one-time programmable
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| D | nintendo-otp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Nintendo Wii and Wii U OTP driver
5 * This is a driver exposing the OTP of a Nintendo Wii or Wii U console.
7 * This memory contains common and per-console keys, signatures and
10 * Based on reversed documentation from https://wiiubrew.org/wiki/Hardware/OTP
19 #include <linux/nvmem-provider.h>
39 .name = "wii-otp",
40 .num_banks = 1,
44 .name = "wiiu-otp",
56 while (words--) { in nintendo_otp_reg_read()
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| /kernel/linux/linux-5.10/drivers/nvmem/ |
| D | rockchip-otp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip OTP Driver
6 * Author: Finley Xiao <finley.xiao@rock-chips.com>
15 #include <linux/nvmem-provider.h>
22 /* OTP Register Offsets */
35 /* OTP Register bits and masks */
41 #define OTPC_SBPI_DONE BIT(1)
67 "otp", "apb_pclk", "phy",
74 static int rockchip_otp_reset(struct rockchip_otp *otp) in rockchip_otp_reset() argument
78 ret = reset_control_assert(otp->rst); in rockchip_otp_reset()
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| D | mxs-ocotp.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale MXS On-Chip OTP driver
15 #include <linux/nvmem-provider.h>
36 static int mxs_ocotp_wait(struct mxs_ocotp *otp) in mxs_ocotp_wait() argument
41 while (timeout--) { in mxs_ocotp_wait()
42 status = readl(otp->base); in mxs_ocotp_wait()
51 return -EBUSY; in mxs_ocotp_wait()
53 return -EIO; in mxs_ocotp_wait()
61 struct mxs_ocotp *otp = context; in mxs_ocotp_read() local
65 ret = clk_enable(otp->clk); in mxs_ocotp_read()
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| D | lpc18xx_otp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * NXP LPC18xx/43xx OTP memory NVMEM driver
10 * TODO: add support for writing OTP register via API in boot ROM.
15 #include <linux/nvmem-provider.h>
22 * LPC18xx OTP memory contains 4 banks with 4 32-bit words. Bank 0 starts
27 * Bank 1/2 is generale purpose or AES key storage for secure devices.
44 struct lpc18xx_otp *otp = context; in lpc18xx_otp_read() local
50 if (count > (LPC18XX_OTP_SIZE - index)) in lpc18xx_otp_read()
51 count = LPC18XX_OTP_SIZE - index; in lpc18xx_otp_read()
54 *buf++ = readl(otp->base + i * LPC18XX_OTP_WORD_SIZE); in lpc18xx_otp_read()
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| /kernel/linux/linux-5.10/drivers/mfd/ |
| D | ab3100-otp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2007-2009 ST-Ericsson AB
6 * Driver to read out OTP from the AB3100 Mixed-signal circuit
19 /* The OTP registers */
33 * @locked: whether the OTP is locked, after locking, no more bits
35 * to change bits from 1->0.
36 * @freq: clocking frequency for the OTP, this frequency is either
37 * 32768Hz or 1MHz/30
62 static int __init ab3100_otp_read(struct ab3100_otp *otp) in ab3100_otp_read() argument
68 err = abx500_get_register_interruptible(otp->dev, 0, in ab3100_otp_read()
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/nvmem/ |
| D | rockchip,otp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/rockchip,otp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip internal OTP (One Time Programmable) memory
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,px30-otp
16 - rockchip,rk3308-otp
17 - rockchip,rk3588-otp
20 maxItems: 1
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| D | lpc1850-otp.txt | 1 * NXP LPC18xx OTP memory
3 Internal OTP (One Time Programmable) memory for NXP LPC18xx/43xx devices.
6 - compatible: Should be "nxp,lpc1850-otp"
7 - reg: Must contain an entry with the physical base address and length
8 for each entry in reg-names.
9 - address-cells: must be set to 1.
10 - size-cells: must be set to 1.
15 otp: otp@40045000 {
16 compatible = "nxp,lpc1850-otp";
18 #address-cells = <1>;
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| D | nintendo-otp.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/nvmem/nintendo-otp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nintendo Wii and Wii U OTP
10 This binding represents the OTP memory as found on a Nintendo Wii or Wii U,
11 which contains common and per-console keys, signatures and related data
14 See https://wiiubrew.org/wiki/Hardware/OTP
17 - Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
20 - $ref: nvmem.yaml#
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| /kernel/linux/linux-6.6/drivers/net/wireless/intel/iwlwifi/ |
| D | iwl-eeprom-read.c | 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2005-2014, 2018-2019, 2021 Intel Corporation
9 #include "iwl-drv.h"
10 #include "iwl-debug.h"
11 #include "iwl-eeprom-read.h"
12 #include "iwl-io.h"
13 #include "iwl-prph.h"
14 #include "iwl-csr.h"
19 * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG.
22 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/nvmem/ |
| D | rockchip-otp.txt | 1 Rockchip internal OTP (One Time Programmable) memory device tree bindings
4 - compatible: Should be one of the following.
5 - "rockchip,px30-otp" - for PX30 SoCs.
6 - "rockchip,rk3308-otp" - for RK3308 SoCs.
7 - reg: Should contain the registers location and size
8 - clocks: Must contain an entry for each entry in clock-names.
9 - clock-names: Should be "otp", "apb_pclk" and "phy".
10 - resets: Must contain an entry for each entry in reset-names.
12 - reset-names: Should be "phy".
17 otp: otp@ff290000 {
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| D | lpc1850-otp.txt | 1 * NXP LPC18xx OTP memory
3 Internal OTP (One Time Programmable) memory for NXP LPC18xx/43xx devices.
6 - compatible: Should be "nxp,lpc1850-otp"
7 - reg: Must contain an entry with the physical base address and length
8 for each entry in reg-names.
9 - address-cells: must be set to 1.
10 - size-cells: must be set to 1.
15 otp: otp@40045000 {
16 compatible = "nxp,lpc1850-otp";
18 #address-cells = <1>;
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| /kernel/linux/linux-5.10/drivers/net/wireless/intel/iwlwifi/ |
| D | iwl-eeprom-read.c | 8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2018 - 2019 Intel Corporation
25 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
29 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
30 * Copyright(c) 2018 - 2019 Intel Corporation
63 #include "iwl-drv.h"
64 #include "iwl-debug.h"
65 #include "iwl-eeprom-read.h"
66 #include "iwl-io.h"
67 #include "iwl-prph.h"
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mtd/ |
| D | mtd.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
19 User-defined MTD device name. Can be used to assign user friendly
24 '#address-cells':
27 '#size-cells':
34 - compatible
37 "@[0-9a-f]+$":
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| /kernel/linux/linux-6.6/drivers/net/wireless/mediatek/mt76/mt7615/ |
| D | eeprom.c | 1 // SPDX-License-Identifier: ISC
25 return -ETIMEDOUT; in mt7615_efuse_read()
50 if (is_mt7663(&dev->mt76)) in mt7615_efuse_init()
57 dev->mt76.otp.data = devm_kzalloc(dev->mt76.dev, len, GFP_KERNEL); in mt7615_efuse_init()
58 dev->mt76.otp.size = len; in mt7615_efuse_init()
59 if (!dev->mt76.otp.data) in mt7615_efuse_init()
60 return -ENOMEM; in mt7615_efuse_init()
62 buf = dev->mt76.otp.data; in mt7615_efuse_init()
80 ret = mt76_eeprom_init(&dev->mt76, MT7615_EEPROM_FULL_SIZE); in mt7615_eeprom_load()
89 u16 val = get_unaligned_le16(dev->eeprom.data); in mt7615_check_eeprom()
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| /kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7615/ |
| D | eeprom.c | 1 // SPDX-License-Identifier: ISC
25 return -ETIMEDOUT; in mt7615_efuse_read()
54 dev->mt76.otp.data = devm_kzalloc(dev->mt76.dev, len, GFP_KERNEL); in mt7615_efuse_init()
55 dev->mt76.otp.size = len; in mt7615_efuse_init()
56 if (!dev->mt76.otp.data) in mt7615_efuse_init()
57 return -ENOMEM; in mt7615_efuse_init()
59 buf = dev->mt76.otp.data; in mt7615_efuse_init()
75 ret = mt76_eeprom_init(&dev->mt76, MT7615_EEPROM_FULL_SIZE); in mt7615_eeprom_load()
84 u16 val = get_unaligned_le16(dev->eeprom.data); in mt7615_check_eeprom()
92 return -EINVAL; in mt7615_check_eeprom()
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| /kernel/linux/linux-6.6/drivers/mtd/spi-nor/ |
| D | otp.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * OTP support for SPI NOR flashes
10 #include <linux/mtd/spi-nor.h>
14 #define spi_nor_otp_region_len(nor) ((nor)->params->otp.org->len)
15 #define spi_nor_otp_n_regions(nor) ((nor)->params->otp.org->n_regions)
18 * spi_nor_otp_read_secr() - read security register
27 * an one-time-programmable memory area, consisting of multiple bytes (usually
28 * 256). Thus one "security register" maps to one OTP region.
34 * Return: number of bytes read successfully, -errno otherwise
43 read_opcode = nor->read_opcode; in spi_nor_otp_read_secr()
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| /kernel/linux/linux-6.6/drivers/net/wireless/mediatek/mt76/mt7603/ |
| D | eeprom.c | 1 // SPDX-License-Identifier: ISC
21 return -ETIMEDOUT; in mt7603_efuse_read()
51 dev->mt76.otp.data = devm_kzalloc(dev->mt76.dev, len, GFP_KERNEL); in mt7603_efuse_init()
52 dev->mt76.otp.size = len; in mt7603_efuse_init()
53 if (!dev->mt76.otp.data) in mt7603_efuse_init()
54 return -ENOMEM; in mt7603_efuse_init()
56 buf = dev->mt76.otp.data; in mt7603_efuse_init()
100 MT_EE_TX_POWER_0_START_2G + 1, in mt7603_apply_cal_free_data()
102 MT_EE_TX_POWER_1_START_2G + 1, in mt7603_apply_cal_free_data()
104 struct device_node *np = dev->mt76.dev->of_node; in mt7603_apply_cal_free_data()
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| /kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7603/ |
| D | eeprom.c | 1 // SPDX-License-Identifier: ISC
21 return -ETIMEDOUT; in mt7603_efuse_read()
51 dev->mt76.otp.data = devm_kzalloc(dev->mt76.dev, len, GFP_KERNEL); in mt7603_efuse_init()
52 dev->mt76.otp.size = len; in mt7603_efuse_init()
53 if (!dev->mt76.otp.data) in mt7603_efuse_init()
54 return -ENOMEM; in mt7603_efuse_init()
56 buf = dev->mt76.otp.data; in mt7603_efuse_init()
100 MT_EE_TX_POWER_0_START_2G + 1, in mt7603_apply_cal_free_data()
102 MT_EE_TX_POWER_1_START_2G + 1, in mt7603_apply_cal_free_data()
104 struct device_node *np = dev->mt76.dev->of_node; in mt7603_apply_cal_free_data()
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| /kernel/linux/linux-5.10/include/linux/mfd/wm831x/ |
| D | otp.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/linux/mfd/wm831x/otp.h -- OTP interface for WM831x
17 * R30720 (0x7800) - Unique ID 1
19 #define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
20 #define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
21 #define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
24 * R30721 (0x7801) - Unique ID 2
26 #define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
27 #define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
28 #define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
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