p15 (full) in projects: kernel - OpenGrok search results

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Searched full:p15 (Results 1 – 25 of 436) sorted by relevance

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/kernel/linux/linux-5.10/arch/arm/mm/
D	proc-mohawk.S	`41 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 44 mcr p15, 0, r0, c1, c0, 0 @ disable caches 62 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 63 mcr p15, 0, ip, c7, c10, 4 @ drain WB 64 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 65 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 68 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 81 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 82 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt 92 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache [all …]`
D	proc-arm946.S	`43 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 46 mcr p15, 0, r0, c1, c0, 0 @ disable caches 57 mcr p15, 0, ip, c7, c5, 0 @ flush I cache 58 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 59 mcr p15, 0, ip, c7, c10, 4 @ drain WB 60 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 63 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 73 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 103 mcr p15, 0, ip, c7, c6, 0 @ flush D cache [all …]`
D	proc-arm926.S	`50 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 53 mcr p15, 0, r0, c1, c0, 0 @ disable caches 69 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 70 mcr p15, 0, ip, c7, c10, 4 @ drain WB 72 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 74 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 77 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 90 mrc p15, 0, r1, c1, c0, 0 @ Read control register 91 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 96 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache [all …]`
D	proc-v7.S	`32 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 35 mcr p15, 0, r0, c1, c0, 0 @ disable caches 55 mrc p15, 0, r2, c1, c0, 0 @ ctrl register 58 mcr p15, 0, r2, c1, c0, 0 @ disable MMU 86 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 116 mcr p15, 0, r3, c7, c5, 0 @ ICIALLU 121 mcr p15, 0, r3, c7, c5, 6 @ flush BTAC/BTB 134 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID 135 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID 138 mrc p15, 0, r6, c3, c0, 0 @ Domain ID [all …]`
D	proc-v6.S	`39 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 42 mcr p15, 0, r0, c1, c0, 0 @ disable caches 57 mrc p15, 0, r1, c1, c0, 0 @ ctrl register 59 mcr p15, 0, r1, c1, c0, 0 @ disable MMU 61 mcr p15, 0, r1, c7, c5, 4 @ ISB 75 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode 76 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt 80 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 102 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 103 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer [all …]`
D	proc-arm940.S	`36 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 39 mcr p15, 0, r0, c1, c0, 0 @ disable caches 50 mcr p15, 0, ip, c7, c5, 0 @ flush I cache 51 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 52 mcr p15, 0, ip, c7, c10, 4 @ drain WB 53 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 56 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 66 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 76 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 108 mcr p15, 0, ip, c7, c6, 0 @ flush D cache [all …]`
D	proc-feroceon.S	`47 mrc p15, 0, r0, c0, c0, 1 @ read cache type register 68 mcr p15, 1, r0, c15, c9, 0 @ clean L2 69 mcr p15, 0, r0, c7, c10, 4 @ drain WB 72 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 75 mcr p15, 0, r0, c1, c0, 0 @ disable caches 91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 92 mcr p15, 0, ip, c7, c10, 4 @ drain WB 94 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 96 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 99 mcr p15, 0, ip, c1, c0, 0 @ ctrl register [all …]`
D	proc-arm1020.S	`66 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 69 mcr p15, 0, r0, c1, c0, 0 @ disable caches 85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 86 mcr p15, 0, ip, c7, c10, 4 @ drain WB 88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 90 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 93 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 141 mcr p15, 0, ip, c7, c10, 4 @ drain WB [all …]`
D	proc-arm925.S	`81 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 84 mcr p15, 0, r0, c1, c0, 0 @ disable caches 109 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 110 mcr p15, 0, ip, c7, c10, 4 @ drain WB 112 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 114 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 117 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 128 mrc p15, 0, r1, c1, c0, 0 @ Read control register 129 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 131 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache [all …]`
D	proc-xsc3.S	56 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 68 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line 89 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 92 mcr p15, 0, r0, c1, c0, 0 @ disable caches 109 mrc p15, 0, r1, c1, c0, 0 @ ctrl register 112 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 113 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB 115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 118 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs 149 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache [all …]
D	proc-arm920.S	`58 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 61 mcr p15, 0, r0, c1, c0, 0 @ disable caches 77 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 78 mcr p15, 0, ip, c7, c10, 4 @ drain WB 80 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 82 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 85 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 95 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 108 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 132 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index [all …]`
D	proc-xscale.S	`69 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 75 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 91 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 93 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 95 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 97 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 116 mrc p15, 0, r1, c1, c0, 1 118 mcr p15, 0, r1, c1, c0, 1 125 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 128 mcr p15, 0, r0, c1, c0, 0 @ disable caches [all …]`
D	proc-fa526.S	`36 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 39 mcr p15, 0, r0, c1, c0, 0 @ disable caches 58 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 59 mcr p15, 0, ip, c7, c10, 4 @ drain WB 61 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 63 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 67 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 83 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 87 mcr p15, 0, r0, c7, c10, 4 @ drain WB 104 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache [all …]`
/kernel/linux/linux-6.6/arch/arm/mm/
D	proc-mohawk.S	`41 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 44 mcr p15, 0, r0, c1, c0, 0 @ disable caches 62 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 63 mcr p15, 0, ip, c7, c10, 4 @ drain WB 64 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 65 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 68 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 81 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 82 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt 92 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache [all …]`
D	proc-arm946.S	`43 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 46 mcr p15, 0, r0, c1, c0, 0 @ disable caches 57 mcr p15, 0, ip, c7, c5, 0 @ flush I cache 58 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 59 mcr p15, 0, ip, c7, c10, 4 @ drain WB 60 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 63 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 73 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 103 mcr p15, 0, ip, c7, c6, 0 @ flush D cache [all …]`
D	proc-arm926.S	`50 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 53 mcr p15, 0, r0, c1, c0, 0 @ disable caches 69 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 70 mcr p15, 0, ip, c7, c10, 4 @ drain WB 72 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 74 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 77 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 90 mrc p15, 0, r1, c1, c0, 0 @ Read control register 91 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 96 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache [all …]`
D	proc-v7.S	`34 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 37 mcr p15, 0, r0, c1, c0, 0 @ disable caches 57 mrc p15, 0, r2, c1, c0, 0 @ ctrl register 60 mcr p15, 0, r2, c1, c0, 0 @ disable MMU 88 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 118 mcr p15, 0, r3, c7, c5, 0 @ ICIALLU 123 mcr p15, 0, r3, c7, c5, 6 @ flush BTAC/BTB 136 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID 137 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID 140 mrc p15, 0, r6, c3, c0, 0 @ Domain ID [all …]`
D	proc-v6.S	`41 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 44 mcr p15, 0, r0, c1, c0, 0 @ disable caches 59 mrc p15, 0, r1, c1, c0, 0 @ ctrl register 61 mcr p15, 0, r1, c1, c0, 0 @ disable MMU 63 mcr p15, 0, r1, c7, c5, 4 @ ISB 77 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode 78 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt 82 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 104 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 105 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer [all …]`
D	proc-arm940.S	`36 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 39 mcr p15, 0, r0, c1, c0, 0 @ disable caches 50 mcr p15, 0, ip, c7, c5, 0 @ flush I cache 51 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 52 mcr p15, 0, ip, c7, c10, 4 @ drain WB 53 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 56 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 66 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 76 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 108 mcr p15, 0, ip, c7, c6, 0 @ flush D cache [all …]`
D	proc-feroceon.S	`47 mrc p15, 0, r0, c0, c0, 1 @ read cache type register 72 mcr p15, 1, r0, c15, c9, 0 @ clean L2 73 mcr p15, 0, r0, c7, c10, 4 @ drain WB 76 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 79 mcr p15, 0, r0, c1, c0, 0 @ disable caches 95 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 96 mcr p15, 0, ip, c7, c10, 4 @ drain WB 98 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 100 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 103 mcr p15, 0, ip, c1, c0, 0 @ ctrl register [all …]`
D	proc-arm1020.S	`66 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 69 mcr p15, 0, r0, c1, c0, 0 @ disable caches 85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 86 mcr p15, 0, ip, c7, c10, 4 @ drain WB 88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 90 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 93 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 141 mcr p15, 0, ip, c7, c10, 4 @ drain WB [all …]`
D	proc-arm925.S	`81 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 84 mcr p15, 0, r0, c1, c0, 0 @ disable caches 109 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 110 mcr p15, 0, ip, c7, c10, 4 @ drain WB 112 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 114 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 117 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 128 mrc p15, 0, r1, c1, c0, 0 @ Read control register 129 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 131 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache [all …]`
D	proc-xsc3.S	56 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 68 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line 89 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 92 mcr p15, 0, r0, c1, c0, 0 @ disable caches 109 mrc p15, 0, r1, c1, c0, 0 @ ctrl register 112 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 113 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB 115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 118 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs 149 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache [all …]
D	proc-arm920.S	`58 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 61 mcr p15, 0, r0, c1, c0, 0 @ disable caches 77 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 78 mcr p15, 0, ip, c7, c10, 4 @ drain WB 80 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 82 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 85 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 95 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 108 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 132 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index [all …]`
D	proc-xscale.S	`69 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 75 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 91 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 93 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 95 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 97 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 116 mrc p15, 0, r1, c1, c0, 1 118 mcr p15, 0, r1, c1, c0, 1 125 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 128 mcr p15, 0, r0, c1, c0, 0 @ disable caches [all …]`

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