| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | spear600.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <0>;
13 #size-cells = <0>;
16 compatible = "arm,arm926ej-s";
27 #address-cells = <1>;
28 #size-cells = <1>;
29 compatible = "simple-bus";
32 vic0: interrupt-controller@f1100000 {
[all …]
|
| D | spear320.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #address-cells = <1>;
13 #size-cells = <1>;
14 compatible = "simple-bus";
19 compatible = "st,spear320-pinmux";
21 #gpio-range-cells = <3>;
28 interrupt-parent = <&shirq>;
33 compatible = "st,spear600-fsmc-nand";
34 #address-cells = <1>;
35 #size-cells = <1>;
[all …]
|
| D | spear310.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #address-cells = <1>;
13 #size-cells = <1>;
14 compatible = "simple-bus";
20 compatible = "st,spear310-pinmux";
22 #gpio-range-cells = <3>;
26 compatible = "st,spear600-fsmc-nand";
27 #address-cells = <1>;
28 #size-cells = <1>;
30 0x40000000 0x0010 /* NAND Base DATA */
[all …]
|
| /kernel/linux/linux-5.10/drivers/irqchip/ |
| D | irq-sni-exiu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for Socionext External Interrupt Unit (EXIU)
5 * Copyright (c) 2017-2019 Linaro, Ltd. <ard.biesheuvel@linaro.org>
7 * Based on irq-tegra.c:
12 #include <linux/interrupt.h>
22 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 void __iomem *base; member
44 writel(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_ack()
53 * EOI or the interrupt will be jammed on. Of course if a level in exiu_irq_eoi()
54 * triggered interrupt is still asserted then the write will not clear in exiu_irq_eoi()
[all …]
|
| D | irq-bcm2835.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 * If an interrupt fires on bank 1 that isn't in the shortcuts list, bit 8
9 * on bank 0 is set to signify that an interrupt in bank 1 has fired, and
12 * If an interrupt fires on bank 1 that _is_ in the shortcuts list, its
13 * shortcut bit in bank 0 is set as well as its interrupt bit in the bank 1
18 * In a proper cascaded interrupt controller, the interrupt lines with
19 * cascaded interrupt controllers on them are just normal interrupt lines.
30 * Bits 0-6: IRQ (index in order of interrupts from banks 1, 2, then 0)
34 * An interrupt must be disabled before configuring it for FIQ generation
80 void __iomem *base; member
[all …]
|
| D | irq-owl-sirq.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Actions Semi Owl SoCs SIRQ interrupt controller driver
6 * David Liu <liuwei@actions-semi.com>
14 #include <linux/interrupt.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 /* S900 SIRQ control register offsets, relative to controller base address */
45 /* INTC_EXTCTL reg offsets relative to controller base address */
51 void __iomem *base; member
98 val = readl_relaxed(data->base + data->params->reg_offset[index]); in owl_sirq_read_extctl()
99 if (data->params->reg_shared) in owl_sirq_read_extctl()
[all …]
|
| D | irq-al-fic.c | 1 // SPDX-License-Identifier: GPL-2.0
28 MODULE_DESCRIPTION("Amazon's Annapurna Labs Interrupt Controller Driver");
38 void __iomem *base; member
50 u32 control = readl_relaxed(fic->base + AL_FIC_CONTROL); in al_fic_set_trigger()
59 gc->chip_types->handler = handler; in al_fic_set_trigger()
60 fic->state = new_state; in al_fic_set_trigger()
61 writel_relaxed(control, fic->base + AL_FIC_CONTROL); in al_fic_set_trigger()
67 struct al_fic *fic = gc->private; in al_fic_irq_set_type()
76 ret = -EINVAL; in al_fic_irq_set_type()
92 if (fic->state == AL_FIC_UNCONFIGURED) { in al_fic_irq_set_type()
[all …]
|
| /kernel/linux/linux-6.6/drivers/irqchip/ |
| D | irq-sni-exiu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for Socionext External Interrupt Unit (EXIU)
5 * Copyright (c) 2017-2019 Linaro, Ltd. <ard.biesheuvel@linaro.org>
7 * Based on irq-tegra.c:
12 #include <linux/interrupt.h>
22 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 void __iomem *base; member
44 writel(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_ack()
53 * EOI or the interrupt will be jammed on. Of course if a level in exiu_irq_eoi()
54 * triggered interrupt is still asserted then the write will not clear in exiu_irq_eoi()
[all …]
|
| D | irq-bcm2835.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 * If an interrupt fires on bank 1 that isn't in the shortcuts list, bit 8
9 * on bank 0 is set to signify that an interrupt in bank 1 has fired, and
12 * If an interrupt fires on bank 1 that _is_ in the shortcuts list, its
13 * shortcut bit in bank 0 is set as well as its interrupt bit in the bank 1
18 * In a proper cascaded interrupt controller, the interrupt lines with
19 * cascaded interrupt controllers on them are just normal interrupt lines.
30 * Bits 0-6: IRQ (index in order of interrupts from banks 1, 2, then 0)
34 * An interrupt must be disabled before configuring it for FIQ generation
80 void __iomem *base; member
[all …]
|
| D | irq-al-fic.c | 1 // SPDX-License-Identifier: GPL-2.0
28 MODULE_DESCRIPTION("Amazon's Annapurna Labs Interrupt Controller Driver");
37 void __iomem *base; member
49 u32 control = readl_relaxed(fic->base + AL_FIC_CONTROL); in al_fic_set_trigger()
58 gc->chip_types->handler = handler; in al_fic_set_trigger()
59 fic->state = new_state; in al_fic_set_trigger()
60 writel_relaxed(control, fic->base + AL_FIC_CONTROL); in al_fic_set_trigger()
66 struct al_fic *fic = gc->private; in al_fic_irq_set_type()
75 ret = -EINVAL; in al_fic_irq_set_type()
91 if (fic->state == AL_FIC_UNCONFIGURED) { in al_fic_irq_set_type()
[all …]
|
| D | irq-owl-sirq.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Actions Semi Owl SoCs SIRQ interrupt controller driver
6 * David Liu <liuwei@actions-semi.com>
14 #include <linux/interrupt.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 /* S900 SIRQ control register offsets, relative to controller base address */
45 /* INTC_EXTCTL reg offsets relative to controller base address */
51 void __iomem *base; member
98 val = readl_relaxed(data->base + data->params->reg_offset[index]); in owl_sirq_read_extctl()
99 if (data->params->reg_shared) in owl_sirq_read_extctl()
[all …]
|
| /kernel/linux/linux-6.6/arch/arm/boot/dts/st/ |
| D | spear600.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <0>;
13 #size-cells = <0>;
16 compatible = "arm,arm926ej-s";
27 #address-cells = <1>;
28 #size-cells = <1>;
29 compatible = "simple-bus";
32 vic0: interrupt-controller@f1100000 {
[all …]
|
| D | spear320.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #address-cells = <1>;
13 #size-cells = <1>;
14 compatible = "simple-bus";
19 compatible = "st,spear320-pinmux";
21 #gpio-range-cells = <3>;
28 interrupt-parent = <&shirq>;
33 compatible = "st,spear600-fsmc-nand";
34 #address-cells = <1>;
35 #size-cells = <1>;
[all …]
|
| D | spear310.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #address-cells = <1>;
13 #size-cells = <1>;
14 compatible = "simple-bus";
20 compatible = "st,spear310-pinmux";
22 #gpio-range-cells = <3>;
26 compatible = "st,spear600-fsmc-nand";
27 #address-cells = <1>;
28 #size-cells = <1>;
30 0x40000000 0x0010 /* NAND Base DATA */
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/dsa/ |
| D | marvell.txt | 2 ---------------------------------------
17 which is at a different MDIO base address in different switch families.
18 - "marvell,mv88e6085" : Switch has base address 0x10. Use with models:
22 - "marvell,mv88e6190" : Switch has base address 0x00. Use with models:
24 - "marvell,mv88e6250" : Switch has base address 0x08 or 0x18. Use with model:
28 - compatible : Should be one of "marvell,mv88e6085",
31 - reg : Address on the MII bus for the switch.
35 - reset-gpios : Should be a gpio specifier for a reset line
36 - interrupts : Interrupt from the switch
37 - interrupt-controller : Indicates the switch is itself an interrupt
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/dsa/ |
| D | marvell.txt | 2 ---------------------------------------
17 which is at a different MDIO base address in different switch families.
18 - "marvell,mv88e6085" : Switch has base address 0x10. Use with models:
22 - "marvell,mv88e6190" : Switch has base address 0x00. Use with models:
24 - "marvell,mv88e6250" : Switch has base address 0x08 or 0x18. Use with model:
28 - compatible : Should be one of "marvell,mv88e6085",
31 - reg : Address on the MII bus for the switch.
35 - reset-gpios : Should be a gpio specifier for a reset line
36 - interrupts : Interrupt from the switch
37 - interrupt-controller : Indicates the switch is itself an interrupt
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | loongson,pch-pic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/interrupt-controller/loongson,pch-pic.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 This interrupt controller is found in the Loongson LS7A family of PCH for
14 transforming interrupts from on-chip devices into HyperTransport vectorized
19 const: loongson,pch-pic-1.0
24 loongson,pic-base-vec:
26 u32 value of the base of parent HyperTransport vector allocated
[all …]
|
| D | socionext,synquacer-exiu.txt | 1 Socionext SynQuacer External Interrupt Unit (EXIU)
3 The Socionext Synquacer SoC has an external interrupt unit (EXIU)
5 level-high type GICv3 SPIs.
9 - compatible : Should be "socionext,synquacer-exiu".
10 - reg : Specifies base physical address and size of the
12 - interrupt-controller : Identifies the node as an interrupt controller.
13 - #interrupt-cells : Specifies the number of cells needed to encode an
14 interrupt source. The value must be 3.
15 - socionext,spi-base : The SPI number of the first SPI of the 32 adjacent
20 - Only SPIs can use the EXIU as an interrupt parent.
[all …]
|
| D | loongson,pch-msi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 This interrupt controller is found in the Loongson LS7A family of PCH for
19 const: loongson,pch-msi-1.0
24 loongson,msi-base-vec:
26 u32 value of the base of parent HyperTransport vector allocated
32 loongson,msi-num-vecs:
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/ |
| D | loongson,pch-pic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-pic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 This interrupt controller is found in the Loongson LS7A family of PCH for
14 transforming interrupts from on-chip devices into HyperTransport vectorized
19 const: loongson,pch-pic-1.0
24 loongson,pic-base-vec:
26 u32 value of the base of parent HyperTransport vector allocated
[all …]
|
| D | loongson,pch-msi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 This interrupt controller is found in the Loongson LS7A family of PCH for
19 const: loongson,pch-msi-1.0
24 loongson,msi-base-vec:
26 u32 value of the base of parent HyperTransport vector allocated
32 loongson,msi-num-vecs:
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | altera-pcie.txt | 4 - compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0"
5 - reg: a list of physical base address and length for TXS and CRA.
6 For "altr,pcie-root-port-2.0", additional HIP base address and length.
7 - reg-names: must include the following entries:
10 "Hip": Hard IP region (if "altr,pcie-root-port-2.0")
11 - interrupts: specifies the interrupt source of the parent interrupt
12 controller. The format of the interrupt specifier depends
13 on the parent interrupt controller.
14 - device_type: must be "pci"
15 - #address-cells: set to <3>
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/ |
| D | altera-pcie.txt | 4 - compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0"
5 - reg: a list of physical base address and length for TXS and CRA.
6 For "altr,pcie-root-port-2.0", additional HIP base address and length.
7 - reg-names: must include the following entries:
10 "Hip": Hard IP region (if "altr,pcie-root-port-2.0")
11 - interrupts: specifies the interrupt source of the parent interrupt
12 controller. The format of the interrupt specifier depends
13 on the parent interrupt controller.
14 - device_type: must be "pci"
15 - #address-cells: set to <3>
[all …]
|
| /kernel/linux/linux-5.10/drivers/i2c/busses/ |
| D | i2c-stm32f4.c | 1 // SPDX-License-Identifier: GPL-2.0
13 * This driver is based on i2c-st.c
21 #include <linux/interrupt.h>
31 #include "i2c-stm32.h"
97 * struct stm32f4_i2c_msg - client specific data
98 * @addr: 8-bit slave addr, including r/w bit
113 * struct stm32f4_i2c_dev - private data of the controller
116 * @base: virtual memory area
120 * @parent_rate: I2C clock parent rate in MHz
126 void __iomem *base; member
[all …]
|
| /kernel/linux/linux-6.6/drivers/i2c/busses/ |
| D | i2c-stm32f4.c | 1 // SPDX-License-Identifier: GPL-2.0
13 * This driver is based on i2c-st.c
21 #include <linux/interrupt.h>
31 #include "i2c-stm32.h"
97 * struct stm32f4_i2c_msg - client specific data
98 * @addr: 8-bit slave addr, including r/w bit
113 * struct stm32f4_i2c_dev - private data of the controller
116 * @base: virtual memory area
120 * @parent_rate: I2C clock parent rate in MHz
126 void __iomem *base; member
[all …]
|