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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/
Dsamsung,pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
12 - Tomasz Figa <tomasz.figa@gmail.com>
15 This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin
22 - External GPIO interrupts (see interrupts property in pin controller node);
24 - External wake-up interrupts - multiplexed (capable of waking up the system
25 see interrupts property in external wake-up interrupt controller node -
[all …]
Dmarvell,dove-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
4 part and usage.
7 - compatible: "marvell,dove-pinctrl"
8 - clocks: (optional) phandle of pdma clock
9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
11 Available mpp pins/groups and functions:
12 Note: brackets (x) are not part of the mpp name for marvell,function and given
16 name pins functions
19 mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu*
23 uart1(cts), lcd-spi(cs1), pmu*
[all …]
Dsamsung,pinctrl-pins-cfg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl-pins-cfg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C/S5P/Exynos SoC pin controller - pins configuration
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
12 - Tomasz Figa <tomasz.figa@gmail.com>
15 This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin
18 Pins configuration for Samsung S3C/S5P/Exynos SoC pin controller.
[all …]
Dfsl,imx51-pinctrl.txt3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx51-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
11 pull-up for this pin. Please refer to imx51 datasheet for the valid pad
15 PAD_CTL_HVE (1 << 13)
16 PAD_CTL_HYS (1 << 8)
17 PAD_CTL_PKE (1 << 7)
18 PAD_CTL_PUE (1 << 6)
20 PAD_CTL_PUS_47K_UP (1 << 4)
[all …]
Dfsl,imx53-pinctrl.txt3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx53-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
11 pull-up for this pin. Please refer to imx53 datasheet for the valid pad
15 PAD_CTL_HVE (1 << 13)
16 PAD_CTL_HYS (1 << 8)
17 PAD_CTL_PKE (1 << 7)
18 PAD_CTL_PUE (1 << 6)
20 PAD_CTL_PUS_47K_UP (1 << 4)
[all …]
Dfsl,imx50-pinctrl.txt3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx50-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
11 pull-up for this pin. Please refer to imx50 datasheet for the valid pad
15 PAD_CTL_HVE (1 << 13)
16 PAD_CTL_HYS (1 << 8)
17 PAD_CTL_PKE (1 << 7)
18 PAD_CTL_PUE (1 << 6)
20 PAD_CTL_PUS_47K_UP (1 << 4)
[all …]
Dfsl,imx35-pinctrl.txt3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx35-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
11 pull-up for this pin. Please refer to imx35 datasheet for the valid pad
15 PAD_CTL_DRIVE_VOLAGAGE_18 (1 << 13)
17 PAD_CTL_HYS (1 << 8)
18 PAD_CTL_PKE (1 << 7)
19 PAD_CTL_PUE (1 << 6)
21 PAD_CTL_PUS_47K_UP (1 << 4)
[all …]
Dfsl,imx6q-pinctrl.txt3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx6q-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
11 pull-up for this pin. Please refer to imx6q datasheet for the valid pad
15 PAD_CTL_HYS (1 << 16)
17 PAD_CTL_PUS_47K_UP (1 << 14)
20 PAD_CTL_PUE (1 << 13)
21 PAD_CTL_PKE (1 << 12)
22 PAD_CTL_ODE (1 << 11)
[all …]
Dfsl,imx6dl-pinctrl.txt3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx6dl-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
11 pull-up for this pin. Please refer to imx6dl datasheet for the valid pad
15 PAD_CTL_HYS (1 << 16)
17 PAD_CTL_PUS_47K_UP (1 << 14)
20 PAD_CTL_PUE (1 << 13)
21 PAD_CTL_PKE (1 << 12)
22 PAD_CTL_ODE (1 << 11)
[all …]
Dfsl,vf610-pinctrl.txt3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,vf610-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is
11 such as pull-up, speed, ode for this pin. Please refer to Vybrid VF610
15 PAD_CTL_SPEED_LOW (1 << 12)
18 PAD_CTL_SRE_FAST (1 << 11)
20 PAD_CTL_ODE (1 << 10)
21 PAD_CTL_HYS (1 << 9)
23 PAD_CTL_DSE_150ohm (1 << 6)
[all …]
Dfsl,imx6sl-pinctrl.txt3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx6sl-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
11 pull-up for this pin. Please refer to imx6sl datasheet for the valid pad
15 PAD_CTL_LVE (1 << 22)
16 PAD_CTL_HYS (1 << 16)
18 PAD_CTL_PUS_47K_UP (1 << 14)
21 PAD_CTL_PUE (1 << 13)
22 PAD_CTL_PKE (1 << 12)
[all …]
Dmarvell,orion-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
4 part and usage.
7 - compatible: "marvell,88f5181-pinctrl",
8 "marvell,88f5181l-pinctrl",
9 "marvell,88f5182-pinctrl",
10 "marvell,88f5281-pinctrl"
12 - reg: two register areas, the first one describing the first two
16 Available mpp pins/groups and functions:
17 Note: brackets (x) are not part of the mpp name for marvell,function and given
22 name pins functions
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/samsung/
Dpinctrl-exynos.h1 /* SPDX-License-Identifier: GPL-2.0+ */
41 #define EXYNOS_EINT_LEVEL_HIGH 1
51 #define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \ argument
55 .nr_pins = pins, \
60 #define EXYNOS_PIN_BANK_EINTG(pins, reg, id, offs) \ argument
64 .nr_pins = pins, \
70 #define EXYNOS_PIN_BANK_EINTW(pins, reg, id, offs) \ argument
74 .nr_pins = pins, \
80 #define EXYNOS5433_PIN_BANK_EINTG(pins, reg, id, offs) \ argument
84 .nr_pins = pins, \
[all …]
/kernel/linux/linux-6.6/drivers/pinctrl/samsung/
Dpinctrl-exynos.h1 /* SPDX-License-Identifier: GPL-2.0+ */
44 #define EXYNOS_EINT_LEVEL_HIGH 1
54 #define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \ argument
58 .nr_pins = pins, \
63 #define EXYNOS_PIN_BANK_EINTG(pins, reg, id, offs) \ argument
67 .nr_pins = pins, \
73 #define EXYNOS_PIN_BANK_EINTW(pins, reg, id, offs) \ argument
77 .nr_pins = pins, \
83 #define EXYNOS5433_PIN_BANK_EINTG(pins, reg, id, offs) \ argument
87 .nr_pins = pins, \
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dmarvell,dove-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
4 part and usage.
7 - compatible: "marvell,dove-pinctrl"
8 - clocks: (optional) phandle of pdma clock
9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
11 Available mpp pins/groups and functions:
12 Note: brackets (x) are not part of the mpp name for marvell,function and given
16 name pins functions
19 mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu*
23 uart1(cts), lcd-spi(cs1), pmu*
[all …]
Dfsl,imx7d-pinctrl.txt3 iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar
4 as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low
5 power state retention capabilities on gpios that are part of iomuxc-lpsr
6 (GPIO1_IO7..GPIO1_IO0). While iomuxc-lpsr provides its own set of registers for
8 iomuxc controller for daisy chain settings, the fsl,input-sel property extends
9 fsl,imx-pinctrl driver to support iomuxc-lpsr controller.
11 iomuxc_lpsr: iomuxc-lpsr@302c0000 {
12 compatible = "fsl,imx7d-iomuxc-lpsr";
14 fsl,input-sel = <&iomuxc>;
18 compatible = "fsl,imx7d-iomuxc";
[all …]
Dfsl,imx50-pinctrl.txt3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx50-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
11 pull-up for this pin. Please refer to imx50 datasheet for the valid pad
15 PAD_CTL_HVE (1 << 13)
16 PAD_CTL_HYS (1 << 8)
17 PAD_CTL_PKE (1 << 7)
18 PAD_CTL_PUE (1 << 6)
20 PAD_CTL_PUS_47K_UP (1 << 4)
[all …]
Dfsl,imx51-pinctrl.txt3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx51-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
11 pull-up for this pin. Please refer to imx51 datasheet for the valid pad
15 PAD_CTL_HVE (1 << 13)
16 PAD_CTL_HYS (1 << 8)
17 PAD_CTL_PKE (1 << 7)
18 PAD_CTL_PUE (1 << 6)
20 PAD_CTL_PUS_47K_UP (1 << 4)
[all …]
Dfsl,imx53-pinctrl.txt3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx53-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
11 pull-up for this pin. Please refer to imx53 datasheet for the valid pad
15 PAD_CTL_HVE (1 << 13)
16 PAD_CTL_HYS (1 << 8)
17 PAD_CTL_PKE (1 << 7)
18 PAD_CTL_PUE (1 << 6)
20 PAD_CTL_PUS_47K_UP (1 << 4)
[all …]
Dfsl,imx35-pinctrl.txt3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx35-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
11 pull-up for this pin. Please refer to imx35 datasheet for the valid pad
15 PAD_CTL_DRIVE_VOLAGAGE_18 (1 << 13)
17 PAD_CTL_HYS (1 << 8)
18 PAD_CTL_PKE (1 << 7)
19 PAD_CTL_PUE (1 << 6)
21 PAD_CTL_PUS_47K_UP (1 << 4)
[all …]
Dfsl,imx6q-pinctrl.txt3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx6q-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
11 pull-up for this pin. Please refer to imx6q datasheet for the valid pad
15 PAD_CTL_HYS (1 << 16)
17 PAD_CTL_PUS_47K_UP (1 << 14)
20 PAD_CTL_PUE (1 << 13)
21 PAD_CTL_PKE (1 << 12)
22 PAD_CTL_ODE (1 << 11)
[all …]
Dfsl,imx6dl-pinctrl.txt3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx6dl-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
11 pull-up for this pin. Please refer to imx6dl datasheet for the valid pad
15 PAD_CTL_HYS (1 << 16)
17 PAD_CTL_PUS_47K_UP (1 << 14)
20 PAD_CTL_PUE (1 << 13)
21 PAD_CTL_PKE (1 << 12)
22 PAD_CTL_ODE (1 << 11)
[all …]
Dfsl,vf610-pinctrl.txt3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,vf610-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is
11 such as pull-up, speed, ode for this pin. Please refer to Vybrid VF610
15 PAD_CTL_SPEED_LOW (1 << 12)
18 PAD_CTL_SRE_FAST (1 << 11)
20 PAD_CTL_ODE (1 << 10)
21 PAD_CTL_HYS (1 << 9)
23 PAD_CTL_DSE_150ohm (1 << 6)
[all …]
Dfsl,imx6sl-pinctrl.txt3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx6sl-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
11 pull-up for this pin. Please refer to imx6sl datasheet for the valid pad
15 PAD_CTL_LVE (1 << 22)
16 PAD_CTL_HYS (1 << 16)
18 PAD_CTL_PUS_47K_UP (1 << 14)
21 PAD_CTL_PUE (1 << 13)
22 PAD_CTL_PKE (1 << 12)
[all …]
Dmarvell,orion-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
4 part and usage.
7 - compatible: "marvell,88f5181-pinctrl",
8 "marvell,88f5181l-pinctrl",
9 "marvell,88f5182-pinctrl",
10 "marvell,88f5281-pinctrl"
12 - reg: two register areas, the first one describing the first two
16 Available mpp pins/groups and functions:
17 Note: brackets (x) are not part of the mpp name for marvell,function and given
22 name pins functions
[all …]

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