| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/ |
| D | qcom,pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
15 PCIe IP.
20 - enum:
21 - qcom,pcie-apq8064
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| D | fsl,imx6q-pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX6 PCIe Endpoint controller
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
14 This PCIe controller is based on the Synopsys DesignWare PCIe IP and
15 thus inherits all the common properties defined in snps,dw-pcie-ep.yaml.
22 - fsl,imx8mm-pcie-ep
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| D | fsl,imx6q-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX6 PCIe host controller
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
14 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
15 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
19 See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree
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| D | hisilicon,kirin-pcie.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: HiSilicon Kirin SoCs PCIe host DT description
10 - Xiaowei Song <songxiaowei@hisilicon.com>
11 - Binghui Wang <wangbinghui@hisilicon.com>
14 Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
15 It shares common functions with the PCIe DesignWare core driver and
17 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
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| D | socionext,uniphier-pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe endpoint controller
10 UniPhier PCIe endpoint controller is based on the Synopsys DesignWare
11 PCI core. It shares common features with the PCIe DesignWare core and
13 Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-pcie-ep
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| D | fsl,imx6q-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX6 PCIe RC/EP controller
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
14 Generic Freescale i.MX PCIe Root Port and Endpoint controller
20 maxItems: 4
22 clock-names:
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| D | socionext,uniphier-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe host controller
10 UniPhier PCIe host controller is based on the Synopsys DesignWare
11 PCI core. It shares common features with the PCIe DesignWare core and
13 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 - $ref: /schemas/pci/snps,dw-pcie.yaml#
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| /kernel/linux/linux-5.10/arch/powerpc/sysdev/ |
| D | fsl_pci.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
19 #define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
22 #define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */
23 #define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */
26 #define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */
40 __be32 potar; /* 0x.0 - Outbound translation address register */
41 __be32 potear; /* 0x.4 - Outbound translation extended address register */
42 __be32 powbar; /* 0x.8 - Outbound window base address register */
43 u8 res1[4];
44 __be32 powar; /* 0x.10 - Outbound window attributes register */
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| /kernel/linux/linux-6.6/arch/powerpc/sysdev/ |
| D | fsl_pci.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
19 #define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
22 #define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */
23 #define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */
26 #define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */
40 __be32 potar; /* 0x.0 - Outbound translation address register */
41 __be32 potear; /* 0x.4 - Outbound translation extended address register */
42 __be32 powbar; /* 0x.8 - Outbound window base address register */
43 u8 res1[4];
44 __be32 powar; /* 0x.10 - Outbound window attributes register */
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | rcar-pci.txt | 1 * Renesas R-Car PCIe interface
4 compatible: "renesas,pcie-r8a7742" for the R8A7742 SoC;
5 "renesas,pcie-r8a7743" for the R8A7743 SoC;
6 "renesas,pcie-r8a7744" for the R8A7744 SoC;
7 "renesas,pcie-r8a774a1" for the R8A774A1 SoC;
8 "renesas,pcie-r8a774b1" for the R8A774B1 SoC;
9 "renesas,pcie-r8a774c0" for the R8A774C0 SoC;
10 "renesas,pcie-r8a7779" for the R8A7779 SoC;
11 "renesas,pcie-r8a7790" for the R8A7790 SoC;
12 "renesas,pcie-r8a7791" for the R8A7791 SoC;
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| D | uniphier-pcie.txt | 1 Socionext UniPhier PCIe host controller bindings
3 This describes the devicetree bindings for PCIe host controller implemented
6 UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core.
7 It shares common functions with the PCIe DesignWare core driver and inherits
9 Documentation/devicetree/bindings/pci/designware-pcie.txt.
12 - compatible: Should be "socionext,uniphier-pcie".
13 - reg: Specifies offset and length of the register set for the device.
14 According to the reg-names, appropriate register sets are required.
15 - reg-names: Must include the following entries:
16 "dbi" - controller configuration registers
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| D | kirin-pcie.txt | 1 HiSilicon Kirin SoCs PCIe host DT description
3 Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
4 It shares common functions with the PCIe DesignWare core driver and
6 Documentation/devicetree/bindings/pci/designware-pcie.txt.
11 - compatible:
12 "hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC
13 - reg: Should contain rc_dbi, apb, phy, config registers location and length.
14 - reg-names: Must include the following entries:
18 "config": PCIe configuration space registers.
19 - reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | qcom,sc8280xp-qmp-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
10 - Vinod Koul <vkoul@kernel.org>
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
19 - qcom,sa8775p-qmp-gen4x2-pcie-phy
20 - qcom,sa8775p-qmp-gen4x4-pcie-phy
21 - qcom,sc8180x-qmp-pcie-phy
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| /kernel/linux/linux-6.6/drivers/pci/controller/ |
| D | pcie-iproc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
9 #include <linux/pci-ecam.h>
17 #include <linux/irqchip/arm-gic-v3.h>
24 #include "pcie-iproc.h"
69 #define MAX_NUM_OB_WINDOW_SIZES 4
91 * struct iproc_pcie_ob_map - iProc PCIe outbound mapping controller-specific
128 .nr_sizes = 4,
133 .nr_sizes = 4,
138 * enum iproc_pcie_ib_map_type - iProc PCIe inbound mapping type
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| D | pci-tegra.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for Tegra SoCs
8 * Based on NVIDIA PCIe driver
9 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 * Bits taken from arch/arm/mach-dove/pcie.c
82 #define AFI_MSI_VEC(x) (0x6c + ((x) * 4))
83 #define AFI_MSI_EN_VEC(x) (0x8c + ((x) * 4))
100 #define AFI_INTR_MASTER_ABORT 4
119 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4)
129 #define AFI_INTR_EN_TGT_WRERR (1 << 4)
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| D | pci-aardvark.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the Aardvark PCIe controller, used on Marvell Armada
20 #include <linux/pci-ecam.h>
30 #include "../pci-bridge-emul.h"
32 /* PCIe core registers */
55 #define PIO_COMPLETION_STATUS_CA 4
92 #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4)
113 #define PCIE_ISR1_POWER_STATE_CHANGE BIT(4)
125 /* PCIe window configuration */
140 #define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4)
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| /kernel/linux/linux-5.10/drivers/pci/controller/ |
| D | pcie-iproc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
16 #include <linux/irqchip/arm-gic-v3.h>
24 #include "pcie-iproc.h"
77 #define MAX_NUM_OB_WINDOW_SIZES 4
99 * iProc PCIe outbound mapping controller specific parameters
136 .nr_sizes = 4,
141 .nr_sizes = 4,
146 * iProc PCIe inbound mapping type
160 * iProc PCIe inbound mapping controller specific parameters
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| D | pci-tegra.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for Tegra SoCs
8 * Based on NVIDIA PCIe driver
9 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 * Bits taken from arch/arm/mach-dove/pcie.c
114 #define AFI_INTR_MASTER_ABORT 4
133 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4)
143 #define AFI_INTR_EN_TGT_WRERR (1 << 4)
176 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4)
270 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | mvebu-gated-clock.txt | 12 -----------------------------------
14 1 pex0_en PCIe 0 Clock out
15 2 pex1_en PCIe 1 Clock out
17 4 ge0 Gigabit Ethernet 0
18 5 pex0 PCIe Cntrl 0
19 9 pex1 PCIe Cntrl 1
29 -----------------------------------
32 4 ptp PTP
33 5 pex0 PCIe 0 Clock out
34 6 pex1 PCIe 1 Clock out
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | mvebu-gated-clock.txt | 12 -----------------------------------
14 1 pex0_en PCIe 0 Clock out
15 2 pex1_en PCIe 1 Clock out
17 4 ge0 Gigabit Ethernet 0
18 5 pex0 PCIe Cntrl 0
19 9 pex1 PCIe Cntrl 1
29 -----------------------------------
32 4 ptp PTP
33 5 pex0 PCIe 0 Clock out
34 6 pex1 PCIe 1 Clock out
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| /kernel/linux/linux-6.6/drivers/pci/controller/dwc/ |
| D | pcie-qcom.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm PCIe root complex driver
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
27 #include <linux/phy/pcie.h>
35 #include "pcie-designware.h"
79 #define AUX_PWR_DET BIT(4)
113 #define BYPASS BIT(4)
154 #define QCOM_PCIE_1_0_0_MAX_CLOCKS 4
171 #define QCOM_PCIE_2_3_2_MAX_CLOCKS 4
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| /kernel/linux/linux-5.10/drivers/pci/controller/mobiveil/ |
| D | pcie-mobiveil.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Mobiveil PCIe Host controller
18 #include "pcie-mobiveil.h"
21 * mobiveil_pcie_sel_page - routine to access paged register
28 static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx) in mobiveil_pcie_sel_page() argument
32 val = readl(pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
36 writel(val, pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
39 static void __iomem *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, in mobiveil_pcie_comp_addr() argument
44 mobiveil_pcie_sel_page(pcie, 0); in mobiveil_pcie_comp_addr()
45 return pcie->csr_axi_slave_base + off; in mobiveil_pcie_comp_addr()
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| /kernel/linux/linux-6.6/drivers/pci/controller/mobiveil/ |
| D | pcie-mobiveil.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Mobiveil PCIe Host controller
18 #include "pcie-mobiveil.h"
21 * mobiveil_pcie_sel_page - routine to access paged register
28 static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx) in mobiveil_pcie_sel_page() argument
32 val = readl(pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
36 writel(val, pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
39 static void __iomem *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, in mobiveil_pcie_comp_addr() argument
44 mobiveil_pcie_sel_page(pcie, 0); in mobiveil_pcie_comp_addr()
45 return pcie->csr_axi_slave_base + off; in mobiveil_pcie_comp_addr()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | nvidia,tegra124-xusb-padctl.txt | 11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
15 ports (e.g. PCIe) and the lanes.
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
34 --------------------
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| D | uncore-other.json | 10 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.…
121 "ScaleUnit": "7.11E-06Bytes",
133 "ScaleUnit": "4Bytes",
145 "ScaleUnit": "4Bytes",
157 "ScaleUnit": "4Bytes",
169 "ScaleUnit": "4Bytes",
184 "ScaleUnit": "4Bytes",
196 "ScaleUnit": "4Bytes",
208 "ScaleUnit": "4Bytes",
220 "ScaleUnit": "4Bytes",
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