| /kernel/linux/linux-6.6/drivers/pci/controller/ |
| D | pcie-rcar-ep.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe endpoint driver for Renesas R-Car SoCs
6 * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
13 #include <linux/pci-epc.h>
17 #include "pcie-rcar.h"
21 /* Structure representing the PCIe interface */
23 struct rcar_pcie pcie; member
33 static void rcar_pcie_ep_hw_init(struct rcar_pcie *pcie) in rcar_pcie_ep_hw_init() argument
37 rcar_pci_write_reg(pcie, 0, PCIETCTLR); in rcar_pcie_ep_hw_init()
40 rcar_pci_write_reg(pcie, 0, PCIEMSR); in rcar_pcie_ep_hw_init()
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| /kernel/linux/linux-5.10/drivers/pci/controller/ |
| D | pcie-rcar-ep.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe endpoint driver for Renesas R-Car SoCs
6 * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
16 #include <linux/pci-epc.h>
20 #include "pcie-rcar.h"
24 /* Structure representing the PCIe interface */
26 struct rcar_pcie pcie; member
36 static void rcar_pcie_ep_hw_init(struct rcar_pcie *pcie) in rcar_pcie_ep_hw_init() argument
40 rcar_pci_write_reg(pcie, 0, PCIETCTLR); in rcar_pcie_ep_hw_init()
43 rcar_pci_write_reg(pcie, 0, PCIEMSR); in rcar_pcie_ep_hw_init()
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| /kernel/linux/linux-5.10/drivers/pci/controller/cadence/ |
| D | pcie-cadence-ep.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe endpoint controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
9 #include <linux/pci-epc.h>
13 #include "pcie-cadence.h"
22 struct cdns_pcie_ep *ep = epc_get_drvdata(epc); in cdns_pcie_ep_write_header() local
23 struct cdns_pcie *pcie = &ep->pcie; in cdns_pcie_ep_write_header() local
25 cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid); in cdns_pcie_ep_write_header()
26 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid); in cdns_pcie_ep_write_header()
27 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code); in cdns_pcie_ep_write_header()
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| D | pcie-cadence-plat.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Cadence PCIe platform driver.
14 #include "pcie-cadence.h"
19 * struct cdns_plat_pcie - private data for this PCIe platform driver
20 * @pcie: Cadence PCIe controller
21 * @is_rc: Set to 1 indicates the PCIe controller mode is Root Complex,
25 struct cdns_pcie *pcie; member
35 static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr) in cdns_plat_cpu_addr_fixup() argument
49 struct device *dev = &pdev->dev; in cdns_plat_pcie_probe()
51 struct cdns_pcie_ep *ep; in cdns_plat_pcie_probe() local
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| /kernel/linux/linux-6.6/drivers/pci/controller/cadence/ |
| D | pcie-cadence-ep.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe endpoint controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
9 #include <linux/pci-epc.h>
13 #include "pcie-cadence.h"
19 static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn) in cdns_pcie_get_fn_from_vfn() argument
27 first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OFFSET); in cdns_pcie_get_fn_from_vfn()
28 stride = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE); in cdns_pcie_get_fn_from_vfn()
29 fn = fn + first_vf_offset + ((vfn - 1) * stride); in cdns_pcie_get_fn_from_vfn()
37 struct cdns_pcie_ep *ep = epc_get_drvdata(epc); in cdns_pcie_ep_write_header() local
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| D | pcie-cadence-plat.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Cadence PCIe platform driver.
13 #include "pcie-cadence.h"
18 * struct cdns_plat_pcie - private data for this PCIe platform driver
19 * @pcie: Cadence PCIe controller
20 * @is_rc: Set to 1 indicates the PCIe controller mode is Root Complex,
24 struct cdns_pcie *pcie; member
34 static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr) in cdns_plat_cpu_addr_fixup() argument
47 struct device *dev = &pdev->dev; in cdns_plat_pcie_probe()
49 struct cdns_pcie_ep *ep; in cdns_plat_pcie_probe() local
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/ |
| D | fsl,imx6q-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX6 PCIe RC/EP controller
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
14 Generic Freescale i.MX PCIe Root Port and Endpoint controller
22 clock-names:
26 num-lanes:
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| D | layerscape-pci.txt | 1 Freescale Layerscape PCIe controller
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 which is used to describe the PLL settings at the time of chip-reset.
10 register available in the Freescale PCIe controller register set,
11 which can allow determining the underlying DesignWare PCIe controller version
15 - compatible: should contain the platform identifier such as:
17 "fsl,ls1021a-pcie"
18 "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
19 "fsl,ls2088a-pcie"
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| D | ti,j721e-pci-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI J721E PCI EP (PCIe Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: cdns-pcie-ep.yaml#
19 - const: ti,j721e-pcie-ep
20 - description: PCIe EP controller in AM64
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| D | fsl,imx6q-pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX6 PCIe Endpoint controller
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
14 This PCIe controller is based on the Synopsys DesignWare PCIe IP and
15 thus inherits all the common properties defined in snps,dw-pcie-ep.yaml.
22 - fsl,imx8mm-pcie-ep
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| D | rcar-pci-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Renesas Electronics Europe GmbH - https://www.renesas.com/eu/en/
4 ---
5 $id: http://devicetree.org/schemas/pci/rcar-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car PCIe Endpoint
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
12 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
17 - enum:
18 - renesas,r8a774a1-pcie-ep # RZ/G2M
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| D | qcom,pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm PCIe Endpoint Controller
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
15 - enum:
16 - qcom,sdx55-pcie-ep
17 - qcom,sm8450-pcie-ep
18 - items:
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| D | socionext,uniphier-pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe endpoint controller
10 UniPhier PCIe endpoint controller is based on the Synopsys DesignWare
11 PCI core. It shares common features with the PCIe DesignWare core and
13 Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-pcie-ep
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| D | ti-pci.txt | 3 PCIe DesignWare Controller
4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
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| D | cdns,cdns-pcie-ep.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence PCIe EP Controller
10 - Tom Joseph <tjoseph@cadence.com>
13 - $ref: cdns-pcie-ep.yaml#
17 const: cdns,cdns-pcie-ep
22 reg-names:
24 - const: reg
[all …]
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| /kernel/linux/linux-5.10/drivers/pci/controller/dwc/ |
| D | pci-layerscape-ep.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe controller EP driver for Freescale Layerscape SoCs
19 #include "pcie-designware.h"
23 #define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
47 ls_pcie_ep_get_features(struct dw_pcie_ep *ep) in ls_pcie_ep_get_features() argument
49 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); in ls_pcie_ep_get_features()
50 struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci); in ls_pcie_ep_get_features() local
52 return pcie->ls_epc; in ls_pcie_ep_get_features()
55 static void ls_pcie_ep_init(struct dw_pcie_ep *ep) in ls_pcie_ep_init() argument
57 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); in ls_pcie_ep_init()
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| D | pci-exynos.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Samsung Exynos SoCs
26 #include "pcie-designware.h"
28 #define to_exynos_pcie(x) dev_get_drvdata((x)->dev)
30 /* PCIe ELBI registers */
56 void __iomem *elbi_base; /* DT 0th resource: PCIe CTRL */
76 struct exynos_pcie *ep);
77 int (*get_clk_resources)(struct exynos_pcie *ep);
78 int (*init_clk_resources)(struct exynos_pcie *ep);
79 void (*deinit_clk_resources)(struct exynos_pcie *ep);
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
23 bool "TI DRA7xx PCIe controller Host Mode"
31 Enables support for the PCIe controller in the DRA7xx SoC to work in
32 host mode. There are two instances of PCIe controller in DRA7xx.
33 This controller can work either as EP or RC. In order to enable
34 host-specific features PCI_DRA7XX_HOST must be selected and in order
35 to enable device-specific features PCI_DRA7XX_EP must be selected.
39 bool "TI DRA7xx PCIe controller Endpoint Mode"
46 Enables support for the PCIe controller in the DRA7xx SoC to work in
47 endpoint mode. There are two instances of PCIe controller in DRA7xx.
[all …]
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| /kernel/linux/linux-6.6/drivers/pci/controller/dwc/ |
| D | pci-layerscape-ep.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe controller EP driver for Freescale Layerscape SoCs
19 #include "pcie-designware.h"
24 /* PEX PFa PCIE PME and message interrupt registers*/
35 #define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
52 static u32 ls_lut_readl(struct ls_pcie_ep *pcie, u32 offset) in ls_lut_readl() argument
54 struct dw_pcie *pci = pcie->pci; in ls_lut_readl()
56 if (pcie->big_endian) in ls_lut_readl()
57 return ioread32be(pci->dbi_base + offset); in ls_lut_readl()
59 return ioread32(pci->dbi_base + offset); in ls_lut_readl()
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| D | pci-exynos.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Samsung Exynos SoCs
5 * Copyright (C) 2013-2020 Samsung Electronics Co., Ltd.
24 #include "pcie-designware.h"
26 #define to_exynos_pcie(x) dev_get_drvdata((x)->dev)
28 /* PCIe ELBI registers */
63 static int exynos_pcie_init_clk_resources(struct exynos_pcie *ep) in exynos_pcie_init_clk_resources() argument
65 struct device *dev = ep->pci.dev; in exynos_pcie_init_clk_resources()
68 ret = clk_prepare_enable(ep->clk); in exynos_pcie_init_clk_resources()
70 dev_err(dev, "cannot enable pcie rc clock"); in exynos_pcie_init_clk_resources()
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 menu "DesignWare-based PCIe controllers"
18 bool "Amazon Annapurna Labs PCIe controller"
24 Say Y here to enable support of the Amazon's Annapurna Labs PCIe
25 controller IP on Amazon SoCs. The PCIe controller uses the DesignWare
27 required only for DT-based platforms. ACPI platforms with the
28 Annapurna Labs PCIe controller don't need to enable this.
31 tristate "Amlogic Meson PCIe controller"
38 and therefore the driver re-uses the DesignWare core functions to
45 bool "Axis ARTPEC-6 PCIe controller (host mode)"
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | rcar-pci-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Renesas Electronics Europe GmbH - https://www.renesas.com/eu/en/
4 ---
5 $id: http://devicetree.org/schemas/pci/rcar-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car PCIe Endpoint
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
12 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
17 - enum:
18 - renesas,r8a774a1-pcie-ep # RZ/G2M
[all …]
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| D | layerscape-pci.txt | 1 Freescale Layerscape PCIe controller
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in designware-pcie.txt.
7 which is used to describe the PLL settings at the time of chip-reset.
10 register available in the Freescale PCIe controller register set,
11 which can allow determining the underlying DesignWare PCIe controller version
15 - compatible: should contain the platform identifier such as:
17 "fsl,ls1021a-pcie"
18 "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
19 "fsl,ls2088a-pcie"
[all …]
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| D | ti-pci.txt | 3 PCIe DesignWare Controller
4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
[all …]
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| D | cdns,cdns-pcie-ep.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence PCIe EP Controller
10 - Tom Joseph <tjoseph@cadence.com>
13 - $ref: "cdns-pcie-ep.yaml#"
14 - $ref: "pci-ep.yaml#"
18 const: cdns,cdns-pcie-ep
23 reg-names:
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