| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | qcom,sc8280xp-qmp-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
10 - Vinod Koul <vkoul@kernel.org>
13 The QMP PHY controller supports physical layer functionality for a number of
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
19 - qcom,sa8775p-qmp-gen4x2-pcie-phy
20 - qcom,sa8775p-qmp-gen4x4-pcie-phy
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| D | hisilicon,phy-hi3670-pcie.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3670-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: HiSilicon Kirin970 PCIe PHY
10 - Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
13 Bindings for PCIe PHY on HiSilicon Kirin 970.
17 const: hisilicon,hi970-pcie-phy
19 "#phy-cells":
20 const: 0
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| D | brcm,cygnus-pcie-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/brcm,cygnus-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Cygnus PCIe PHY
10 - Ray Jui <ray.jui@broadcom.com>
11 - Scott Branden <scott.branden@broadcom.com>
15 pattern: "^pcie[-|_]phy(@.*)?$"
19 - const: brcm,cygnus-pcie-phy
24 Base address and length of the PCIe PHY block
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| D | lantiq,vrx200-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lantiq VRX200 and ARX300 PCIe PHY
10 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
13 "#phy-cells":
15 description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
19 - lantiq,vrx200-pcie-phy
20 - lantiq,arx300-pcie-phy
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| D | socionext,uniphier-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe PHY
10 This describes the devicetree bindings for PHY interface built into
11 PCIe controller implemented on Socionext UniPhier SoCs.
14 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 - socionext,uniphier-pro5-pcie-phy
20 - socionext,uniphier-ld20-pcie-phy
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| D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
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| D | fsl,imx8-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8 SoC series PCIe PHY
10 - Richard Zhu <hongxing.zhu@nxp.com>
13 "#phy-cells":
14 const: 0
18 - fsl,imx8mm-pcie-phy
19 - fsl,imx8mp-pcie-phy
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| /kernel/linux/linux-6.6/drivers/pci/controller/cadence/ |
| D | pcie-cadence.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
9 #include "pcie-cadence.h"
11 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) in cdns_pcie_detect_quiet_min_delay_set() argument
13 u32 delay = 0x3; in cdns_pcie_detect_quiet_min_delay_set()
19 ltssm_control_cap = cdns_pcie_readl(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP); in cdns_pcie_detect_quiet_min_delay_set()
24 cdns_pcie_writel(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP, ltssm_control_cap); in cdns_pcie_detect_quiet_min_delay_set()
27 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, in cdns_pcie_set_outbound_region() argument
35 u64 sz = 1ULL << fls64(size - 1); in cdns_pcie_set_outbound_region()
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| /kernel/linux/linux-5.10/drivers/pci/controller/cadence/ |
| D | pcie-cadence.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
8 #include "pcie-cadence.h"
10 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) in cdns_pcie_detect_quiet_min_delay_set() argument
12 u32 delay = 0x3; in cdns_pcie_detect_quiet_min_delay_set()
18 ltssm_control_cap = cdns_pcie_readl(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP); in cdns_pcie_detect_quiet_min_delay_set()
23 cdns_pcie_writel(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP, ltssm_control_cap); in cdns_pcie_detect_quiet_min_delay_set()
26 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, in cdns_pcie_set_outbound_region() argument
34 u64 sz = 1ULL << fls64(size - 1); in cdns_pcie_set_outbound_region()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | brcm,cygnus-pcie-phy.txt | 1 Broadcom Cygnus PCIe PHY
4 - compatible: must be "brcm,cygnus-pcie-phy"
5 - reg: base address and length of the PCIe PHY block
6 - #address-cells: must be 1
7 - #size-cells: must be 0
9 Each PCIe PHY should be represented by a child node
12 - reg: the PHY ID
13 0 - PCIe RC 0
14 1 - PCIe RC 1
15 - #phy-cells: must be 0
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| D | nvidia,tegra124-xusb-padctl.txt | 11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
15 ports (e.g. PCIe) and the lanes.
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
29 abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
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| D | lantiq,vrx200-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lantiq VRX200 and ARX300 PCIe PHY Device Tree Bindings
10 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
13 "#phy-cells":
15 description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
19 - lantiq,vrx200-pcie-phy
20 - lantiq,arx300-pcie-phy
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| D | qcom,qmp-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm QMP PHY controller
11 - Manu Gautam <mgautam@codeaurora.org>
14 QMP phy controller supports physical layer functionality for a number of
15 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
20 - qcom,ipq8074-qmp-pcie-phy
21 - qcom,ipq8074-qmp-usb3-phy
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| /kernel/linux/linux-6.6/drivers/pci/controller/dwc/ |
| D | pcie-armada8k.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Marvell Armada-8K SoCs
5 * Armada-8K PCIe Glue Layer Source Code
20 #include <linux/phy/phy.h>
25 #include "pcie-designware.h"
33 struct phy *phy[ARMADA8K_PCIE_MAX_LANES]; member
37 #define PCIE_VENDOR_REGS_OFFSET 0x8000
39 #define PCIE_GLOBAL_CONTROL_REG (PCIE_VENDOR_REGS_OFFSET + 0x0)
42 #define PCIE_DEVICE_TYPE_MASK 0xF
43 #define PCIE_DEVICE_TYPE_RC 0x4 /* Root complex */
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| D | pcie-intel-gw.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Intel Gateway SoCs
14 #include <linux/phy/phy.h>
20 #include "pcie-designware.h"
22 #define PORT_AFR_N_FTS_GEN12_DFT (SZ_128 - 1)
26 /* PCIe Application logic Registers */
27 #define PCIE_APP_CCR 0x10
28 #define PCIE_APP_CCR_LTSSM_ENABLE BIT(0)
30 #define PCIE_APP_MSG_CR 0x30
31 #define PCIE_APP_MSG_XMT_PM_TURNOFF BIT(0)
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| D | pcie-kirin.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Kirin Phone SoCs
22 #include <linux/phy/phy.h>
29 #include "pcie-designware.h"
31 #define to_kirin_pcie(x) dev_get_drvdata((x)->dev)
33 /* PCIe ELBI registers */
34 #define SOC_PCIECTRL_CTRL0_ADDR 0x000
35 #define SOC_PCIECTRL_CTRL1_ADDR 0x004
36 #define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21)
39 #define PCIE_APP_LTSSM_ENABLE 0x01c
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| /kernel/linux/linux-5.10/drivers/pci/controller/dwc/ |
| D | pcie-armada8k.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Marvell Armada-8K SoCs
5 * Armada-8K PCIe Glue Layer Source Code
20 #include <linux/phy/phy.h>
26 #include "pcie-designware.h"
34 struct phy *phy[ARMADA8K_PCIE_MAX_LANES]; member
38 #define PCIE_VENDOR_REGS_OFFSET 0x8000
40 #define PCIE_GLOBAL_CONTROL_REG (PCIE_VENDOR_REGS_OFFSET + 0x0)
43 #define PCIE_DEVICE_TYPE_MASK 0xF
44 #define PCIE_DEVICE_TYPE_RC 0x4 /* Root complex */
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | rockchip-pcie-host.txt | 1 * Rockchip AXI PCIe Root Port Bridge DT description
4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
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| D | pci-keystone.txt | 1 TI Keystone PCIe interface
4 hardware version 3.65. It shares common functions with the PCIe DesignWare
6 Documentation/devicetree/bindings/pci/designware-pcie.txt
8 Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt
12 Required Properties:-
14 compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC
15 Should be "ti,am654-pcie-rc" for RC on AM654x SoC
16 reg: Three register ranges as listed in the reg-names property
17 reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
22 interrupt-cells: should be set to 1
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| D | samsung,exynos5440-pcie.txt | 1 * Samsung Exynos 5440 PCIe interface
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in designware-pcie.txt.
7 - compatible: "samsung,exynos5440-pcie"
8 - reg: base addresses and lengths of the PCIe controller,
9 - reg-names : First name should be set to "elbi".
12 NOTE: When using the "config" property, reg-names must be set.
13 - interrupts: A list of interrupt outputs for level interrupt,
15 - phys: From PHY binding. Phandle for the generic PHY.
16 Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt
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| D | brcm,iproc-pcie.txt | 1 * Broadcom iProc PCIe controller with the platform bus interface
4 - compatible:
5 "brcm,iproc-pcie" for the first generation of PAXB based controller,
7 "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based
9 "brcm,iproc-pcie-paxc" for the first generation of PAXC based
11 "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based
13 PAXB-based root complex is used for external endpoint devices. PAXC-based
15 - reg: base address and length of the PCIe controller I/O register space
16 - #interrupt-cells: set to <1>
17 - interrupt-map-mask and interrupt-map, standard PCI properties to define the
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| /kernel/linux/linux-6.6/drivers/pci/controller/ |
| D | pcie-mt7621.c | 1 // SPDX-License-Identifier: GPL-2.0+
12 * support RT2880/RT3883 PCIe
15 * support RT6855/MT7620 PCIe
28 #include <linux/phy/phy.h>
35 /* MediaTek-specific configuration registers */
36 #define PCIE_FTS_NUM 0x70c
38 #define PCIE_FTS_NUM_L0(x) (((x) & 0xff) << 8)
40 /* Host-PCI bridge registers */
41 #define RALINK_PCI_PCICFG_ADDR 0x0000
42 #define RALINK_PCI_PCIMSK_ADDR 0x000c
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| /kernel/linux/linux-5.10/drivers/phy/broadcom/ |
| D | phy-bcm-sr-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Broadcom
12 #include <linux/phy/phy.h>
18 #define SR_PAXC_PHY_IDX (SR_NR_PCIE_PHYS - 1)
20 #define PCIE_PIPEMUX_CFG_OFFSET 0x10c
21 #define PCIE_PIPEMUX_SELECT_STRAP 0xf
23 #define CDRU_STRAP_DATA_LSW_OFFSET 0x5c
25 #define PCIE_PIPEMUX_MASK 0xf
27 #define MHB_MEM_PW_PAXC_OFFSET 0x1c0
28 #define MHB_PWR_ARR_POWERON 0x8
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| /kernel/linux/linux-6.6/drivers/phy/broadcom/ |
| D | phy-bcm-sr-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Broadcom
12 #include <linux/phy/phy.h>
18 #define SR_PAXC_PHY_IDX (SR_NR_PCIE_PHYS - 1)
20 #define PCIE_PIPEMUX_CFG_OFFSET 0x10c
21 #define PCIE_PIPEMUX_SELECT_STRAP 0xf
23 #define CDRU_STRAP_DATA_LSW_OFFSET 0x5c
25 #define PCIE_PIPEMUX_MASK 0xf
27 #define MHB_MEM_PW_PAXC_OFFSET 0x1c0
28 #define MHB_PWR_ARR_POWERON 0x8
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| D | phy-bcm-cygnus-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/phy/phy.h>
11 #define PCIE_CFG_OFFSET 0x00
16 CYGNUS_PHY_PCIE0 = 0,
24 * struct cygnus_pcie_phy - Cygnus PCIe PHY device
25 * @core: pointer to the Cygnus PCIe PHY core control
26 * @id: internal ID to identify the Cygnus PCIe PHY
27 * @phy: pointer to the kernel PHY device
32 struct phy *phy; member
36 * struct cygnus_pcie_phy_core - Cygnus PCIe PHY core control
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