| /kernel/linux/linux-5.10/drivers/clk/ |
| D | clk-xgene.c | 446 struct xgene_clk *pclk = to_xgene_clk(hw); in xgene_clk_enable() local
450 if (pclk->lock) in xgene_clk_enable()
451 spin_lock_irqsave(pclk->lock, flags); in xgene_clk_enable()
453 if (pclk->param.csr_reg) { in xgene_clk_enable()
456 data = xgene_clk_read(pclk->param.csr_reg + in xgene_clk_enable()
457 pclk->param.reg_clk_offset); in xgene_clk_enable()
458 data |= pclk->param.reg_clk_mask; in xgene_clk_enable()
459 xgene_clk_write(data, pclk->param.csr_reg + in xgene_clk_enable()
460 pclk->param.reg_clk_offset); in xgene_clk_enable()
463 pclk->param.reg_clk_offset, pclk->param.reg_clk_mask, in xgene_clk_enable()
[all …]
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| D | clk-stm32mp1.c | 1285 #define PCLK(_id, _name, _parent, _flags, _mgate)\ macro
1796 PCLK(TIM2, "tim2", "pclk1", CLK_IGNORE_UNUSED, G_TIM2),
1797 PCLK(TIM3, "tim3", "pclk1", CLK_IGNORE_UNUSED, G_TIM3),
1798 PCLK(TIM4, "tim4", "pclk1", CLK_IGNORE_UNUSED, G_TIM4),
1799 PCLK(TIM5, "tim5", "pclk1", CLK_IGNORE_UNUSED, G_TIM5),
1800 PCLK(TIM6, "tim6", "pclk1", CLK_IGNORE_UNUSED, G_TIM6),
1801 PCLK(TIM7, "tim7", "pclk1", CLK_IGNORE_UNUSED, G_TIM7),
1802 PCLK(TIM12, "tim12", "pclk1", CLK_IGNORE_UNUSED, G_TIM12),
1803 PCLK(TIM13, "tim13", "pclk1", CLK_IGNORE_UNUSED, G_TIM13),
1804 PCLK(TIM14, "tim14", "pclk1", CLK_IGNORE_UNUSED, G_TIM14),
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/ |
| D | clk-xgene.c | 445 struct xgene_clk *pclk = to_xgene_clk(hw); in xgene_clk_enable() local
449 if (pclk->lock) in xgene_clk_enable()
450 spin_lock_irqsave(pclk->lock, flags); in xgene_clk_enable()
452 if (pclk->param.csr_reg) { in xgene_clk_enable()
455 data = xgene_clk_read(pclk->param.csr_reg + in xgene_clk_enable()
456 pclk->param.reg_clk_offset); in xgene_clk_enable()
457 data |= pclk->param.reg_clk_mask; in xgene_clk_enable()
458 xgene_clk_write(data, pclk->param.csr_reg + in xgene_clk_enable()
459 pclk->param.reg_clk_offset); in xgene_clk_enable()
462 pclk->param.reg_clk_offset, pclk->param.reg_clk_mask, in xgene_clk_enable()
[all …]
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| D | clk-stm32mp1.c | 1379 #define PCLK(_id, _name, _parent, _flags, _mgate)\ macro
1883 PCLK(TIM2, "tim2", "pclk1", CLK_IGNORE_UNUSED, G_TIM2),
1884 PCLK(TIM3, "tim3", "pclk1", CLK_IGNORE_UNUSED, G_TIM3),
1885 PCLK(TIM4, "tim4", "pclk1", CLK_IGNORE_UNUSED, G_TIM4),
1886 PCLK(TIM5, "tim5", "pclk1", CLK_IGNORE_UNUSED, G_TIM5),
1887 PCLK(TIM6, "tim6", "pclk1", CLK_IGNORE_UNUSED, G_TIM6),
1888 PCLK(TIM7, "tim7", "pclk1", CLK_IGNORE_UNUSED, G_TIM7),
1889 PCLK(TIM12, "tim12", "pclk1", CLK_IGNORE_UNUSED, G_TIM12),
1890 PCLK(TIM13, "tim13", "pclk1", CLK_IGNORE_UNUSED, G_TIM13),
1891 PCLK(TIM14, "tim14", "pclk1", CLK_IGNORE_UNUSED, G_TIM14),
[all …]
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| D | clk-conf.c | 18 struct clk *clk, *pclk; in __set_clk_parents() local
40 pclk = of_clk_get_from_provider(&clkspec); in __set_clk_parents()
42 if (IS_ERR(pclk)) { in __set_clk_parents()
43 if (PTR_ERR(pclk) != -EPROBE_DEFER) in __set_clk_parents()
46 return PTR_ERR(pclk); in __set_clk_parents()
68 rc = clk_set_parent(clk, pclk); in __set_clk_parents()
71 __clk_get_name(clk), __clk_get_name(pclk), rc); in __set_clk_parents()
73 clk_put(pclk); in __set_clk_parents()
77 clk_put(pclk); in __set_clk_parents()
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| /kernel/linux/linux-6.6/drivers/clk/x86/ |
| D | clk-pmc-atom.c | 165 struct clk_plt *pclk; in plt_clk_register() local
169 pclk = devm_kzalloc(&pdev->dev, sizeof(*pclk), GFP_KERNEL); in plt_clk_register()
170 if (!pclk) in plt_clk_register()
179 pclk->hw.init = &init; in plt_clk_register()
180 pclk->reg = pmc_data->base + PMC_CLK_CTL_OFFSET + id * PMC_CLK_CTL_SIZE; in plt_clk_register()
181 spin_lock_init(&pclk->lock); in plt_clk_register()
188 if (pmc_data->critical && plt_clk_is_enabled(&pclk->hw)) in plt_clk_register()
191 ret = devm_clk_hw_register(&pdev->dev, &pclk->hw); in plt_clk_register()
193 pclk = ERR_PTR(ret); in plt_clk_register()
197 pclk->lookup = clkdev_hw_create(&pclk->hw, init.name, NULL); in plt_clk_register()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/x86/ |
| D | clk-pmc-atom.c | 165 struct clk_plt *pclk; in plt_clk_register() local
169 pclk = devm_kzalloc(&pdev->dev, sizeof(*pclk), GFP_KERNEL); in plt_clk_register()
170 if (!pclk) in plt_clk_register()
179 pclk->hw.init = &init; in plt_clk_register()
180 pclk->reg = pmc_data->base + PMC_CLK_CTL_OFFSET + id * PMC_CLK_CTL_SIZE; in plt_clk_register()
181 spin_lock_init(&pclk->lock); in plt_clk_register()
188 if (pmc_data->critical && plt_clk_is_enabled(&pclk->hw)) in plt_clk_register()
191 ret = devm_clk_hw_register(&pdev->dev, &pclk->hw); in plt_clk_register()
193 pclk = ERR_PTR(ret); in plt_clk_register()
197 pclk->lookup = clkdev_hw_create(&pclk->hw, init.name, NULL); in plt_clk_register()
[all …]
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| /kernel/linux/linux-5.10/drivers/clocksource/ |
| D | timer-microchip-pit64b.c | 53 * @pclk: PIT64B's peripheral clock
59 struct clk *pclk; member
166 clk_disable_unprepare(timer->pclk); in mchp_pit64b_clkevt_suspend()
173 clk_prepare_enable(timer->pclk); in mchp_pit64b_clkevt_resume()
210 * PIT64B timer may be fed by gclk or pclk. When gclk is used its rate has to
211 * be at least 3 times lower that pclk's rate. pclk rate is fixed, gclk rate
212 * could be changed via clock APIs. The chosen clock (pclk or gclk) could be
217 * requested rate. If PCLK/GCLK < 3 (condition requested by PIT64B hardware)
218 * then the function falls back on using PCLK as clock source for PIT64B timer
229 * | |-->pclk -->|-->| | +---------+ +-----+ |
[all …]
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| D | timer-rockchip.c | 37 struct clk *pclk; member
131 struct clk *pclk; in rk_timer_probe() local
146 pclk = of_clk_get_by_name(np, "pclk"); in rk_timer_probe()
147 if (IS_ERR(pclk)) { in rk_timer_probe()
148 ret = PTR_ERR(pclk); in rk_timer_probe()
149 pr_err("Failed to get pclk for '%s'\n", TIMER_NAME); in rk_timer_probe()
153 ret = clk_prepare_enable(pclk); in rk_timer_probe()
155 pr_err("Failed to enable pclk for '%s'\n", TIMER_NAME); in rk_timer_probe()
158 timer->pclk = pclk; in rk_timer_probe()
191 clk_disable_unprepare(pclk); in rk_timer_probe()
[all …]
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| /kernel/linux/linux-6.6/drivers/clocksource/ |
| D | timer-microchip-pit64b.c | 53 * @pclk: PIT64B's peripheral clock
59 struct clk *pclk; member
140 clk_disable_unprepare(timer->pclk); in mchp_pit64b_suspend()
145 clk_prepare_enable(timer->pclk); in mchp_pit64b_resume()
261 * PIT64B timer may be fed by gclk or pclk. When gclk is used its rate has to
262 * be at least 3 times lower that pclk's rate. pclk rate is fixed, gclk rate
263 * could be changed via clock APIs. The chosen clock (pclk or gclk) could be
268 * requested rate. If PCLK/GCLK < 3 (condition requested by PIT64B hardware)
269 * then the function falls back on using PCLK as clock source for PIT64B timer
280 * | |-->pclk -->|-->| | +---------+ +-----+ |
[all …]
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| D | timer-rockchip.c | 37 struct clk *pclk; member
131 struct clk *pclk; in rk_timer_probe() local
146 pclk = of_clk_get_by_name(np, "pclk"); in rk_timer_probe()
147 if (IS_ERR(pclk)) { in rk_timer_probe()
148 ret = PTR_ERR(pclk); in rk_timer_probe()
149 pr_err("Failed to get pclk for '%s'\n", TIMER_NAME); in rk_timer_probe()
153 ret = clk_prepare_enable(pclk); in rk_timer_probe()
155 pr_err("Failed to enable pclk for '%s'\n", TIMER_NAME); in rk_timer_probe()
158 timer->pclk = pclk; in rk_timer_probe()
191 clk_disable_unprepare(pclk); in rk_timer_probe()
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | versatile-ab.dts | 150 pclk: pclk@24M { label
225 clocks = <&pclk>;
233 clocks = <&xtal24mhz>, <&pclk>;
241 clocks = <&xtal24mhz>, <&pclk>;
249 clocks = <&xtal24mhz>, <&pclk>;
256 clocks = <&pclk>;
263 clocks = <&pclk>;
271 clocks = <&osc1>, <&pclk>;
310 clocks = <&pclk>;
318 clocks = <&pclk>;
[all …]
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| D | ecx-common.dtsi | 50 clocks = <&pclk>;
60 clocks = <&pclk>;
71 clocks = <&pclk>;
82 clocks = <&pclk>;
93 clocks = <&pclk>;
102 clocks = <&pclk>;
110 clocks = <&pclk>;
118 clocks = <&pclk>, <&pclk>;
187 pclk: pclk { label
199 clocks = <&pclk>;
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| D | arm-realview-eb.dtsi | 111 pclk: pclk@0 { label
313 clocks = <&pclk>;
326 clocks = <&mclk>, <&pclk>;
336 clocks = <&kmiclk>, <&pclk>;
343 clocks = <&kmiclk>, <&pclk>;
350 clocks = <&pclk>;
357 clocks = <&uartclk>, <&pclk>;
364 clocks = <&uartclk>, <&pclk>;
371 clocks = <&uartclk>, <&pclk>;
378 clocks = <&uartclk>, <&pclk>;
[all …]
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| D | arm-realview-pbx.dtsi | 126 pclk: pclk@0 { label
355 clocks = <&uartclk>, <&pclk>;
362 clocks = <&uartclk>, <&pclk>;
369 clocks = <&uartclk>, <&pclk>;
376 clocks = <&sspclk>, <&pclk>;
383 clocks = <&wdogclk>, <&pclk>;
391 clocks = <&wdogclk>, <&pclk>;
401 <&pclk>;
412 <&pclk>;
425 clocks = <&pclk>;
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/samsung/ |
| D | clk-s3c64xx.c | 164 DIV(PCLK, "pclk", "hclkx2", CLK_DIV0, 12, 4),
221 GATE_ON(PCLK_SKEY, "pclk_skey", "pclk", PCLK_GATE, 24),
222 GATE_ON(PCLK_CHIPID, "pclk_chipid", "pclk", PCLK_GATE, 23),
223 GATE_BUS(PCLK_SPI1, "pclk_spi1", "pclk", PCLK_GATE, 22),
224 GATE_BUS(PCLK_SPI0, "pclk_spi0", "pclk", PCLK_GATE, 21),
225 GATE_BUS(PCLK_HSIRX, "pclk_hsirx", "pclk", PCLK_GATE, 20),
226 GATE_BUS(PCLK_HSITX, "pclk_hsitx", "pclk", PCLK_GATE, 19),
227 GATE_ON(PCLK_GPIO, "pclk_gpio", "pclk", PCLK_GATE, 18),
228 GATE_BUS(PCLK_IIC0, "pclk_iic0", "pclk", PCLK_GATE, 17),
229 GATE_BUS(PCLK_IIS1, "pclk_iis1", "pclk", PCLK_GATE, 16),
[all …]
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| D | clk-s3c2412.c | 63 DIV(PCLK, "pclk", "hclk", CLKDIVN, 2, 1),
106 GATE(PCLK_WDT, "wdt", "pclk", CLKCON, 28, 0, 0),
107 GATE(PCLK_SPI, "spi", "pclk", CLKCON, 27, 0, 0),
108 GATE(PCLK_I2S, "i2s", "pclk", CLKCON, 26, 0, 0),
109 GATE(PCLK_I2C, "i2c", "pclk", CLKCON, 25, 0, 0),
110 GATE(PCLK_ADC, "adc", "pclk", CLKCON, 24, 0, 0),
111 GATE(PCLK_RTC, "rtc", "pclk", CLKCON, 23, 0, 0),
112 GATE(PCLK_GPIO, "gpio", "pclk", CLKCON, 22, CLK_IGNORE_UNUSED, 0),
113 GATE(PCLK_UART2, "uart2", "pclk", CLKCON, 21, 0, 0),
114 GATE(PCLK_UART1, "uart1", "pclk", CLKCON, 20, 0, 0),
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/samsung/ |
| D | clk-s3c64xx.c | 164 DIV(PCLK, "pclk", "hclkx2", CLK_DIV0, 12, 4),
221 GATE_ON(PCLK_SKEY, "pclk_skey", "pclk", PCLK_GATE, 24),
222 GATE_ON(PCLK_CHIPID, "pclk_chipid", "pclk", PCLK_GATE, 23),
223 GATE_BUS(PCLK_SPI1, "pclk_spi1", "pclk", PCLK_GATE, 22),
224 GATE_BUS(PCLK_SPI0, "pclk_spi0", "pclk", PCLK_GATE, 21),
225 GATE_BUS(PCLK_HSIRX, "pclk_hsirx", "pclk", PCLK_GATE, 20),
226 GATE_BUS(PCLK_HSITX, "pclk_hsitx", "pclk", PCLK_GATE, 19),
227 GATE_ON(PCLK_GPIO, "pclk_gpio", "pclk", PCLK_GATE, 18),
228 GATE_BUS(PCLK_IIC0, "pclk_iic0", "pclk", PCLK_GATE, 17),
229 GATE_BUS(PCLK_IIS1, "pclk_iis1", "pclk", PCLK_GATE, 16),
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/arm/ |
| D | versatile-ab.dts | 161 pclk: pclk@24M { label
236 clocks = <&pclk>;
244 clocks = <&xtal24mhz>, <&pclk>;
252 clocks = <&xtal24mhz>, <&pclk>;
260 clocks = <&xtal24mhz>, <&pclk>;
267 clocks = <&pclk>;
274 clocks = <&pclk>;
282 clocks = <&osc1>, <&pclk>;
321 clocks = <&pclk>;
329 clocks = <&pclk>;
[all …]
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| D | arm-realview-eb.dtsi | 111 pclk: pclk@0 { label
329 clocks = <&pclk>;
342 clocks = <&mclk>, <&pclk>;
352 clocks = <&kmiclk>, <&pclk>;
359 clocks = <&kmiclk>, <&pclk>;
366 clocks = <&pclk>;
373 clocks = <&uartclk>, <&pclk>;
380 clocks = <&uartclk>, <&pclk>;
387 clocks = <&uartclk>, <&pclk>;
394 clocks = <&uartclk>, <&pclk>;
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/hisilicon/ |
| D | clk-hi3620.c | 35 static const char *const uart0_mux_p[] __initconst = { "osc26m", "pclk", };
36 static const char *const uart1_mux_p[] __initconst = { "osc26m", "pclk", };
37 static const char *const uart2_mux_p[] __initconst = { "osc26m", "pclk", };
38 static const char *const uart3_mux_p[] __initconst = { "osc26m", "pclk", };
39 static const char *const uart4_mux_p[] __initconst = { "osc26m", "pclk", };
69 { HI3620_PCLK, "pclk", NULL, 0, 26000000, },
138 { HI3620_RTCCLK, "rtcclk", "pclk", CLK_SET_RATE_PARENT, 0x20, 5, 0, },
139 { HI3620_KPC_CLK, "kpc_clk", "pclk", CLK_SET_RATE_PARENT, 0x20, 6, 0, },
140 { HI3620_GPIOCLK0, "gpioclk0", "pclk", CLK_SET_RATE_PARENT, 0x20, 8, 0, },
141 { HI3620_GPIOCLK1, "gpioclk1", "pclk", CLK_SET_RATE_PARENT, 0x20, 9, 0, },
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/hisilicon/ |
| D | clk-hi3620.c | 34 static const char *const uart0_mux_p[] __initconst = { "osc26m", "pclk", };
35 static const char *const uart1_mux_p[] __initconst = { "osc26m", "pclk", };
36 static const char *const uart2_mux_p[] __initconst = { "osc26m", "pclk", };
37 static const char *const uart3_mux_p[] __initconst = { "osc26m", "pclk", };
38 static const char *const uart4_mux_p[] __initconst = { "osc26m", "pclk", };
68 { HI3620_PCLK, "pclk", NULL, 0, 26000000, },
137 { HI3620_RTCCLK, "rtcclk", "pclk", CLK_SET_RATE_PARENT, 0x20, 5, 0, },
138 { HI3620_KPC_CLK, "kpc_clk", "pclk", CLK_SET_RATE_PARENT, 0x20, 6, 0, },
139 { HI3620_GPIOCLK0, "gpioclk0", "pclk", CLK_SET_RATE_PARENT, 0x20, 8, 0, },
140 { HI3620_GPIOCLK1, "gpioclk1", "pclk", CLK_SET_RATE_PARENT, 0x20, 9, 0, },
[all …]
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| /kernel/linux/linux-5.10/drivers/iio/dac/ |
| D | stm32-dac-core.c | 22 * @pclk: peripheral clock common for all DACs
27 struct clk *pclk; member
64 ret = clk_prepare_enable(priv->pclk); in stm32_dac_core_hw_start()
66 dev_err(dev, "pclk enable failed: %d\n", ret); in stm32_dac_core_hw_start()
83 clk_disable_unprepare(priv->pclk); in stm32_dac_core_hw_stop()
114 regmap = devm_regmap_init_mmio_clk(dev, "pclk", mmio, in stm32_dac_probe()
120 priv->pclk = devm_clk_get(dev, "pclk"); in stm32_dac_probe()
121 if (IS_ERR(priv->pclk)) { in stm32_dac_probe()
122 ret = PTR_ERR(priv->pclk); in stm32_dac_probe()
123 dev_err(dev, "pclk get failed\n"); in stm32_dac_probe()
[all …]
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| /kernel/linux/linux-6.6/drivers/iio/dac/ |
| D | stm32-dac-core.c | 22 * @pclk: peripheral clock common for all DACs
27 struct clk *pclk; member
64 ret = clk_prepare_enable(priv->pclk); in stm32_dac_core_hw_start()
66 dev_err(dev, "pclk enable failed: %d\n", ret); in stm32_dac_core_hw_start()
83 clk_disable_unprepare(priv->pclk); in stm32_dac_core_hw_stop()
112 regmap = devm_regmap_init_mmio_clk(dev, "pclk", mmio, in stm32_dac_probe()
118 priv->pclk = devm_clk_get(dev, "pclk"); in stm32_dac_probe()
119 if (IS_ERR(priv->pclk)) in stm32_dac_probe()
120 return dev_err_probe(dev, PTR_ERR(priv->pclk), "pclk get failed\n"); in stm32_dac_probe()
156 priv->common.hfsel = (clk_get_rate(priv->pclk) > 80000000UL); in stm32_dac_probe()
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/calxeda/ |
| D | ecx-common.dtsi | 50 clocks = <&pclk>;
60 clocks = <&pclk>;
71 clocks = <&pclk>;
82 clocks = <&pclk>;
93 clocks = <&pclk>;
102 clocks = <&pclk>;
110 clocks = <&pclk>;
118 clocks = <&pclk>, <&pclk>;
187 pclk: pclk { label
199 clocks = <&pclk>;
|