| /kernel/linux/linux-5.10/drivers/pinctrl/sunxi/ |
| D | pinctrl-sunxi.h | 6 * Maxime Ripard <maxime.ripard@free-electrons.com>
32 #define SUNXI_PINCTRL_PIN(bank, pin) \ argument
33 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
62 #define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)
66 #define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)
70 #define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
125 struct pinctrl_pin_desc pin; member
149 unsigned pin; member
177 .pin = _pin, \
184 .pin = _pin, \
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/ |
| D | renesas,rza1-ports.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/A1 combined Pin and GPIO controller
10 - Jacopo Mondi <jacopo+renesas@jmondi.org>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
14 The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis
17 writing configuration values to per-port register sets.
[all …]
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| D | brcm,bcm2835-gpio.txt | 7 - compatible: "brcm,bcm2835-gpio"
8 - compatible: should be one of:
9 "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl
10 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
11 "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl
12 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
13 - reg: Should contain the physical address of the GPIO module's registers.
14 - gpio-controller: Marks the device node as a GPIO controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and the
17 - bit 0 specifies polarity (0 for normal, 1 for inverted)
[all …]
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| D | pinctrl-st.txt | 1 *ST pin controller.
3 Each multi-function pin is controlled, driven and routed through the
4 PIO multiplexing block. Each pin supports GPIO functionality (ALT0)
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
6 the pin to different hardware blocks.
8 When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and
12 gpio driver to configure a pin.
14 GPIO bank can have one of the two possible types of interrupt-wirings.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | renesas,rza1-ports.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/A1 combined Pin and GPIO controller
10 - Jacopo Mondi <jacopo+renesas@jmondi.org>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
14 The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis
17 writing configuration values to per-port register sets.
[all …]
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| D | pinctrl-single.txt | 1 One-register-per-pin type device tree based pinctrl driver
4 - compatible : "pinctrl-single" or "pinconf-single".
5 "pinctrl-single" means that pinconf isn't supported.
6 "pinconf-single" means that generic pinconf is supported.
8 - reg : offset and length of the register set for the mux registers
10 - #pinctrl-cells : number of cells in addition to the index, set to 1
11 for pinctrl-single,pins and 2 for pinctrl-single,bits
13 - pinctrl-single,register-width : pinmux register access width in bits
15 - pinctrl-single,function-mask : mask of allowed pinmux function bits
19 - pinctrl-single,function-off : function off mode for disabled state if
[all …]
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| D | brcm,bcm2835-gpio.txt | 7 - compatible: "brcm,bcm2835-gpio"
8 - compatible: should be one of:
9 "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl
10 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
11 "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl
12 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
13 - reg: Should contain the physical address of the GPIO module's registers.
14 - gpio-controller: Marks the device node as a GPIO controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and the
17 - bit 0 specifies polarity (0 for normal, 1 for inverted)
[all …]
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| D | pinctrl-st.txt | 1 *ST pin controller.
3 Each multi-function pin is controlled, driven and routed through the
4 PIO multiplexing block. Each pin supports GPIO functionality (ALT0)
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
6 the pin to different hardware blocks.
8 When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and
12 gpio driver to configure a pin.
14 GPIO bank can have one of the two possible types of interrupt-wirings.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
[all …]
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| /kernel/linux/linux-6.6/include/uapi/sound/ |
| D | snd_sst_tokens.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * snd_sst_tokens.h - Intel SST tokens definition
17 * %SKL_TKN_U8_IN_PIN_TYPE: Input pin type,
20 * %SKL_TKN_U8_OUT_PIN_TYPE: Output pin type,
22 * %SKL_TKN_U8_DYN_IN_PIN: Configure Input pin dynamically
25 * %SKL_TKN_U8_DYN_OUT_PIN: Configure Output pin dynamically
65 * %SKL_TKN_U16_PIN_INST_ID: Stores the pin instance id
96 * formats and the pin count.
99 * the pin count value.
118 * %SKL_TKN_U32_FMT_INTERLEAVE: Interleaving style which can be per
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/i2c/ |
| D | tda1997x.txt | 1 Device-Tree bindings for the NXP TDA1997x HDMI receiver
6 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
8 - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
9 - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
10 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
16 - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/i2c/ |
| D | tda1997x.txt | 1 Device-Tree bindings for the NXP TDA1997x HDMI receiver
6 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
8 - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
9 - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
10 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
16 - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
[all …]
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| /kernel/linux/linux-5.10/drivers/pinctrl/zte/ |
| D | pinctrl-zx.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
11 * struct zx_mux_desc - hardware mux descriptor
21 * struct zx_pin_data - hardware per-pin data
22 * @aon_pin: whether it's an AON pin
31 * arbitrarily, AON pinmux register bits are well organized per pin id, and
32 * each pin occupies two bits, so that we can calculate the AON register offset
33 * and bit position from pin id. Thus, we only need to define TOP pinmux and
34 * AON pinconf register data for the pin.
51 #define TOP_PIN(pin, off, bp, wd, coff, cbp, ...) { \ argument
52 .number = pin, \
[all …]
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| /kernel/linux/linux-5.10/include/uapi/sound/ |
| D | snd_sst_tokens.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * snd_sst_tokens.h - Intel SST tokens definition
27 * %SKL_TKN_U8_IN_PIN_TYPE: Input pin type,
30 * %SKL_TKN_U8_OUT_PIN_TYPE: Output pin type,
32 * %SKL_TKN_U8_DYN_IN_PIN: Configure Input pin dynamically
35 * %SKL_TKN_U8_DYN_OUT_PIN: Configure Output pin dynamically
75 * %SKL_TKN_U16_PIN_INST_ID: Stores the pin instance id
106 * formats and the pin count.
109 * the pin count value.
128 * %SKL_TKN_U32_FMT_INTERLEAVE: Interleaving style which can be per
[all …]
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| /kernel/linux/linux-5.10/drivers/pinctrl/intel/ |
| D | pinctrl-intel.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
26 * struct intel_pingroup - Description about group of pins
32 * @modes: If not %NULL this will hold mode for each pin in @pins
43 * struct intel_function - Description about a function
55 * struct intel_padgroup - Hardware pad group information
57 * @base: Starting pin of this group
74 * enum - Special treatment for GPIO base in pad group
78 * @INTEL_GPIO_BASE_MATCH: matches with starting pin number
81 INTEL_GPIO_BASE_ZERO = -2,
82 INTEL_GPIO_BASE_NOMAP = -1,
[all …]
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| /kernel/linux/linux-6.6/include/linux/pinctrl/ |
| D | pinconf.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
20 * struct pinconf_ops - pin config operations, to be implemented by
21 * pin configuration capable drivers.
22 * @is_generic: for pin controllers that want to use the generic interface,
24 * @pin_config_get: get the config of a certain pin, if the requested config
25 * is not available on this controller this should return -ENOTSUPP
26 * and if it is available but disabled it should return -EINVAL
27 * @pin_config_set: configure an individual pin
[all …]
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| /kernel/linux/linux-5.10/include/linux/pinctrl/ |
| D | pinconf.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
20 * struct pinconf_ops - pin config operations, to be implemented by
21 * pin configuration capable drivers.
22 * @is_generic: for pin controllers that want to use the generic interface,
24 * @pin_config_get: get the config of a certain pin, if the requested config
25 * is not available on this controller this should return -ENOTSUPP
26 * and if it is available but disabled it should return -EINVAL
27 * @pin_config_set: configure an individual pin
[all …]
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| /kernel/linux/linux-5.10/drivers/pinctrl/ |
| D | pinctrl-coh901.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2007-2012 ST-Ericsson AB
6 * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
21 #include <linux/pinctrl/pinconf-generic.h>
22 #include "pinctrl-coh901.h"
27 * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
29 * bit 8-2 (mask 0x000001FC) contains the core version ID.
56 /* 8 bits per port, no version has more than 7 ports */
80 u32 per; member
89 * its context. It calculates the port offset from the given pin
[all …]
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| D | core.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Core private header for the pin control subsystem
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
13 #include <linux/radix-tree.h>
20 * struct pinctrl_dev - pin control class device
21 * @node: node to include this pin controller in the global pin controller list
22 * @desc: the pin controller descriptor supplied when initializing this pin
24 * @pin_desc_tree: each pin descriptor for this pin controller is stored in
26 * @pin_group_tree: optionally each pin group can be stored in this radix tree
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/bridge/ |
| D | adi,adv7511.txt | 2 ------------------------------------------------
11 - compatible: Should be one of:
18 - reg: I2C slave addresses
32 - adi,input-depth: Number of bits per color component at the input (8, 10 or
34 - adi,input-colorspace: The input color space, one of "rgb", "yuv422" or
36 - adi,input-clock: The input clock type, one of "1x" (one clock cycle per
37 pixel), "2x" (two clock cycles per pixel), "ddr" (one clock cycle per pixel,
43 - adi,input-style: The input components arrangement variant (1, 2 or 3), as
45 - adi,input-justification: The input bit justification ("left", "evenly",
48 - avdd-supply: A 1.8V supply that powers up the AVDD pin on the chip.
[all …]
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| /kernel/linux/linux-6.6/drivers/pinctrl/intel/ |
| D | pinctrl-intel.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
26 * struct intel_pingroup - Description about group of pins
27 * @grp: Generic data of the pin group (name and pins)
29 * @modes: If not %NULL this will hold mode for each pin in @pins
38 * struct intel_function - Description about a function
39 * @func: Generic data of the pin function (name and groups of pins)
48 * struct intel_padgroup - Hardware pad group information
50 * @base: Starting pin of this group
67 * enum - Special treatment for GPIO base in pad group
71 * @INTEL_GPIO_BASE_MATCH: matches with starting pin number
[all …]
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| /kernel/linux/linux-5.10/drivers/pinctrl/meson/ |
| D | pinctrl-meson.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Pin controller and GPIO driver for Amlogic Meson SoCs
17 * struct meson_pmx_group - a pinmux group
35 * struct meson_pmx_func - a pinmux function
48 * struct meson_reg_desc - a register descriptor
54 * pull-enable, direction, etc. for a single pin
62 * enum meson_reg_type - type of registers encoded in @meson_reg_desc
75 * enum meson_pinconf_drv - value of drive-strength supported
88 * @first: first pin of the bank
89 * @last: last pin of the bank
[all …]
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| /kernel/linux/linux-6.6/drivers/pinctrl/meson/ |
| D | pinctrl-meson.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Pin controller and GPIO driver for Amlogic Meson SoCs
20 * struct meson_pmx_group - a pinmux group
38 * struct meson_pmx_func - a pinmux function
51 * struct meson_reg_desc - a register descriptor
57 * pull-enable, direction, etc. for a single pin
65 * enum meson_reg_type - type of registers encoded in @meson_reg_desc
78 * enum meson_pinconf_drv - value of drive-strength supported
91 * @first: first pin of the bank
92 * @last: last pin of the bank
[all …]
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| /kernel/linux/linux-6.6/include/linux/ |
| D | ptp_clock_kernel.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
19 * struct ptp_clock_request - request PTP clock event
47 * struct ptp_system_timestamp - system time corresponding to a PHC timestamp
57 * struct ptp_clock_info - describes a PTP hardware clock
63 * @max_adj: The maximum possible frequency adjustment, in parts per billon.
77 * nominal frequency in parts per million, but with a
143 * @verify: Confirm that a pin can perform a given function. The PTP
146 * assumes that every pin can perform every function. This
149 * zero if the function can be assigned to this pin, and
151 * parameter pin: index of the pin in question.
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/bridge/ |
| D | adi,adv7511.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
21 - adi,adv7511
22 - adi,adv7511w
23 - adi,adv7513
37 reg-names:
40 needing a non-default address.
43 - const: main
[all …]
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| /kernel/linux/linux-5.10/include/linux/ |
| D | atmel-mci.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
11 * struct mci_slot_pdata - board-specific per-slot configuration
13 * @detect_pin: GPIO pin wired to the card detect switch
14 * @wp_pin: GPIO pin wired to the write protect sensor
15 * @detect_is_active_high: The state of the detect pin when it is active
23 * Note that support for multiple slots is experimental -- some cards
36 * struct mci_platform_data - board-specific MMC/SDcard configuration
38 * @slot: Per-slot configuration data.
|