Searched +full:peripheral +full:- +full:controller (Results 1 – 25 of 1070) sorted by relevance
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| /kernel/linux/linux-6.6/drivers/usb/gadget/udc/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
4 # (a) a peripheral controller, and
7 # NOTE: Gadget support ** DOES NOT ** depend on host-side CONFIG_USB !!
9 # - Host systems (like PCs) need CONFIG_USB (with "A" jacks).
10 # - Peripherals (like PDAs) need CONFIG_USB_GADGET (with "B" jacks).
11 # - Some systems have both kinds of controllers.
13 # With help from a special transceiver and a "Mini-AB" jack, systems with
14 # both kinds of controller can also support "USB On-the-Go" (CONFIG_USB_OTG).
18 # USB Peripheral Controller Support
22 # - integrated/SOC controllers first
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| /kernel/linux/linux-5.10/drivers/usb/gadget/udc/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
4 # (a) a peripheral controller, and
7 # NOTE: Gadget support ** DOES NOT ** depend on host-side CONFIG_USB !!
9 # - Host systems (like PCs) need CONFIG_USB (with "A" jacks).
10 # - Peripherals (like PDAs) need CONFIG_USB_GADGET (with "B" jacks).
11 # - Some systems have both kinds of controllers.
13 # With help from a special transceiver and a "Mini-AB" jack, systems with
14 # both kinds of controller can also support "USB On-the-Go" (CONFIG_USB_OTG).
18 # USB Peripheral Controller Support
22 # - integrated/SOC controllers first
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| /kernel/linux/linux-6.6/drivers/clk/qcom/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
40 tristate "MSM8916 APCS Clock Controller"
43 Support for the APCS Clock Controller on msm8916 devices. The
49 tristate "MSM8996 CPU Clock Controller"
54 Support for the CPU clock controller on msm8996 devices.
59 tristate "SDX55 and SDX65 APCS Clock Controller"
63 Support for the APCS Clock Controller on SDX55, SDX65 platforms. The
69 tristate "RPM based Clock Controller"
82 tristate "RPM over SMD based Clock Controller"
104 tristate "APQ8084 Global Clock Controller"
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | pistachio-clock.txt | 4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral
6 from the device-tree.
9 ----------------
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
17 Core clock controller:
18 ----------------------
20 The core clock controller generates clocks for the CPU, RPU (WiFi + BT
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | pistachio-clock.txt | 4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral
6 from the device-tree.
9 ----------------
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
17 Core clock controller:
18 ----------------------
20 The core clock controller generates clocks for the CPU, RPU (WiFi + BT
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| /kernel/linux/linux-5.10/drivers/clk/qcom/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
32 tristate "MSM8916 APCS Clock Controller"
35 Support for the APCS Clock Controller on msm8916 devices. The
41 tristate "MSM8996 CPU Clock Controller"
45 Support for the CPU clock controller on msm8996 devices.
50 tristate "RPM based Clock Controller"
63 tristate "RPM over SMD based Clock Controller"
85 tristate "APQ8084 Global Clock Controller"
88 Support for the global clock controller on apq8084 devices.
89 Say Y if you want to use peripheral devices such as UART, SPI,
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | img,pdc-intc.txt | 1 * ImgTec Powerdown Controller (PDC) Interrupt Controller Binding
4 representation of a PDC IRQ controller. This has a number of input interrupt
10 - compatible: Specifies the compatibility list for the interrupt controller.
11 The type shall be <string> and the value shall include "img,pdc-intc".
13 - reg: Specifies the base PDC physical address(s) and size(s) of the
14 addressable register space. The type shall be <prop-encoded-array>.
16 - interrupt-controller: The presence of this property identifies the node
17 as an interrupt controller. No property value shall be defined.
19 - #interrupt-cells: Specifies the number of cells needed to encode an
22 - num-perips: Number of waking peripherals.
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/ |
| D | img,pdc-intc.txt | 1 * ImgTec Powerdown Controller (PDC) Interrupt Controller Binding
4 representation of a PDC IRQ controller. This has a number of input interrupt
10 - compatible: Specifies the compatibility list for the interrupt controller.
11 The type shall be <string> and the value shall include "img,pdc-intc".
13 - reg: Specifies the base PDC physical address(s) and size(s) of the
14 addressable register space. The type shall be <prop-encoded-array>.
16 - interrupt-controller: The presence of this property identifies the node
17 as an interrupt controller. No property value shall be defined.
19 - #interrupt-cells: Specifies the number of cells needed to encode an
22 - num-perips: Number of waking peripherals.
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/ |
| D | mc-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/mc-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a Memory Controller bus.
10 Many Memory Controllers need to add properties to peripheral devices.
11 They could be common properties like reg or they could be controller
13 to be defined in the peripheral node because they are per-peripheral
14 and there can be multiple peripherals attached to a controller. All
15 those properties are listed here. The controller specific properties
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/spi/ |
| D | spi-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
10 Many SPI controllers need to add properties to peripheral devices. They could
11 be common properties like spi-max-frequency, spi-cpha, etc. or they could be
12 controller specific like delay in clock or data lines, etc. These properties
13 need to be defined in the peripheral node because they are per-peripheral and
14 there can be multiple peripherals attached to a controller. All those
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | phy-hi3798cv200-combphy.txt | 4 - compatible: Should be "hisilicon,hi3798cv200-combphy"
5 - reg: Should be the address space for COMBPHY configuration and state
6 registers in peripheral controller, e.g. PERI_COMBPHY0_CFG and
8 - #phy-cells: Should be 1. The cell number is used to select the phy mode
9 as defined in <dt-bindings/phy/phy.h>.
10 - clocks: The phandle to clock provider and clock specifier pair.
11 - resets: The phandle to reset controller and reset specifier pair.
13 Refer to phy/phy-bindings.txt for the generic PHY binding properties.
16 - hisilicon,fixed-mode: If the phy device doesn't support mode select
19 - hisilicon,mode-select-bits: If the phy device support mode select,
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | phy-hi3798cv200-combphy.txt | 4 - compatible: Should be "hisilicon,hi3798cv200-combphy"
5 - reg: Should be the address space for COMBPHY configuration and state
6 registers in peripheral controller, e.g. PERI_COMBPHY0_CFG and
8 - #phy-cells: Should be 1. The cell number is used to select the phy mode
9 as defined in <dt-bindings/phy/phy.h>.
10 - clocks: The phandle to clock provider and clock specifier pair.
11 - resets: The phandle to reset controller and reset specifier pair.
13 Refer to phy/phy-bindings.txt for the generic PHY binding properties.
16 - hisilicon,fixed-mode: If the phy device doesn't support mode select
19 - hisilicon,mode-select-bits: If the phy device support mode select,
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/dma/ |
| D | atmel-xdma.txt | 1 * Atmel Extensible Direct Memory Access Controller (XDMAC)
3 * XDMA Controller
5 - compatible: Should be "atmel,sama5d4-dma", "microchip,sam9x60-dma" or
6 "microchip,sama7g5-dma" or
7 "microchip,sam9x7-dma", "atmel,sama5d4-dma".
8 - reg: Should contain DMA registers location and length.
9 - interrupts: Should contain DMA interrupt.
10 - #dma-cells: Must be <1>, used to represent the number of integer cells in
12 - The 1st cell specifies the channel configuration register:
13 - bit 13: SIF, source interface identifier, used to get the memory
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/ |
| D | atmel-xdma.txt | 1 * Atmel Extensible Direct Memory Access Controller (XDMAC)
3 * XDMA Controller
5 - compatible: Should be "atmel,sama5d4-dma" or "microchip,sam9x60-dma".
6 - reg: Should contain DMA registers location and length.
7 - interrupts: Should contain DMA interrupt.
8 - #dma-cells: Must be <1>, used to represent the number of integer cells in
10 - The 1st cell specifies the channel configuration register:
11 - bit 13: SIF, source interface identifier, used to get the memory
13 - bit 14: DIF, destination interface identifier, used to get the peripheral
15 - bit 30-24: PERID, peripheral identifier.
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| /kernel/linux/linux-6.6/include/soc/canaan/ |
| D | k210-sysctl.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
10 * Kendryte K210 SoC system controller registers offsets.
11 * Taken from Kendryte SDK (kendryte-standalone-sdk).
15 #define K210_SYSCTL_PLL0 0x08 /* PLL0 controller */
16 #define K210_SYSCTL_PLL1 0x0C /* PLL1 controller */
17 #define K210_SYSCTL_PLL2 0x10 /* PLL2 controller */
20 #define K210_SYSCTL_SEL0 0x20 /* Clock select controller 0 */
21 #define K210_SYSCTL_SEL1 0x24 /* Clock select controller 1 */
23 #define K210_SYSCTL_EN_PERI 0x2C /* Peripheral clock enable */
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| /kernel/linux/linux-6.6/drivers/dma/qcom/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
9 controller, as present on MSM8x60, APQ8064, and IPQ8064 devices.
10 This controller provides DMA capabilities for both general purpose
11 and on-chip peripheral devices.
19 Enable support for the QCOM BAM DMA controller. This controller
20 provides DMA capabilities for a variety of on-chip devices.
28 Enable support for the QCOM GPI DMA controller. This controller
29 provides DMA capabilities for a variety of peripheral buses such
32 transfer data between DDR and peripheral.
51 Enable support for the Qualcomm Technologies HIDMA controller.
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| /kernel/linux/linux-5.10/Documentation/driver-api/memory-devices/ |
| D | ti-gpmc.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 GPMC (General Purpose Memory Controller)
7 GPMC is an unified memory controller dedicated to interfacing external
14 * Pseudo-SRAM devices
24 functioning of the peripheral, while peripheral has another set of
25 timings. To have peripheral work with gpmc, peripheral timings has to
27 translated depends on the connected peripheral. Also there is a
32 from gpmc peripheral timings. struct gpmc_device_timings fields has to
33 be updated with timings from the datasheet of the peripheral that is
34 connected to gpmc. A few of the peripheral timings can be fed either
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| /kernel/linux/linux-6.6/Documentation/driver-api/memory-devices/ |
| D | ti-gpmc.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 GPMC (General Purpose Memory Controller)
7 GPMC is an unified memory controller dedicated to interfacing external
14 * Pseudo-SRAM devices
24 functioning of the peripheral, while peripheral has another set of
25 timings. To have peripheral work with gpmc, peripheral timings has to
27 translated depends on the connected peripheral. Also there is a
32 from gpmc peripheral timings. struct gpmc_device_timings fields has to
33 be updated with timings from the datasheet of the peripheral that is
34 connected to gpmc. A few of the peripheral timings can be fed either
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | atmel,at91-pinctrl.txt | 1 * Atmel AT91 Pinmux Controller
3 The AT91 Pinmux Controller, enables the IC
7 different PAD settings (like pull up, keeper, etc) the controller controls
10 Please refer to pinctrl-bindings.txt in this directory for details of the
18 such as pull-up, multi drive, etc.
20 Required properties for iomux controller:
21 - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
22 or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl"
23 - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
28 Each column will represent the possible peripheral of the pinctrl
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/ |
| D | atmel,at91-pinctrl.txt | 1 * Atmel AT91 Pinmux Controller
3 The AT91 Pinmux Controller, enables the IC
7 different PAD settings (like pull up, keeper, etc) the controller controls
10 Please refer to pinctrl-bindings.txt in this directory for details of the
18 such as pull-up, multi drive, etc.
20 Required properties for iomux controller:
21 - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
22 or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl"
23 - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
28 Each column will represent the possible peripheral of the pinctrl
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/socionext/ |
| D | socionext,uniphier-perictrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-perictrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier peripheral block controller
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
13 Peripheral block implemented on Socionext UniPhier SoCs is an integrated
15 Peripheral block controller is a logic to control the component.
20 - enum:
21 - socionext,uniphier-ld4-perictrl
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/spmi/ |
| D | qcom,spmi-pmic-arb.txt | 1 Qualcomm SPMI Controller (PMIC Arbiter)
4 controller with wrapping arbitration logic to allow for multiple on-chip
7 The PMIC Arbiter can also act as an interrupt controller, providing interrupts
11 controller binding requirements for child nodes.
13 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
14 generic interrupt controller binding documentation.
17 - compatible : should be "qcom,spmi-pmic-arb".
18 - reg-names : must contain:
19 "core" - core registers
20 "intr" - interrupt controller registers
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| /kernel/linux/linux-6.6/drivers/usb/cdns3/ |
| D | Kconfig | 8 dual-role controller.
9 It supports: dual-role switch, Host-only, and Peripheral-only.
17 tristate "Cadence USB3 Dual-Role Controller"
20 Say Y here if your system has a Cadence USB3 dual-role controller.
21 It supports: dual-role switch, Host-only, and Peripheral-only.
30 bool "Cadence USB3 device controller"
33 Say Y here to enable device controller functionality of the
34 Cadence USBSS-DEV driver.
36 This controller supports FF, HS and SS mode. It doesn't support
40 bool "Cadence USB3 host controller"
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/can/ |
| D | st,stm32-bxcan.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/st,stm32-bxcan.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics bxCAN controller
9 description: STMicroelectronics BxCAN controller for CAN bus
12 - Dario Binacchi <dario.binacchi@amarulasolutions.com>
15 - $ref: can-controller.yaml#
20 - st,stm32f4-bxcan
22 st,can-primary:
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/ |
| D | cdns,usb3.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence USBSS-DRD controller bindings
10 - Pawel Laszczak <pawell@cadence.com>
18 - description: OTG controller registers
19 - description: XHCI Host controller registers
20 - description: DEVICE controller registers
22 reg-names:
24 - const: otg
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