| /kernel/linux/linux-5.10/drivers/iio/frequency/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 # Phase-Locked Loop (PLL) frequency synthesizers
27 # Phase-Locked Loop (PLL) frequency synthesizers
30 menu "Phase-Locked Loop (PLL) frequency synthesizers"
|
| /kernel/linux/linux-6.6/Documentation/ABI/testing/ |
| D | sysfs-driver-zynqmp-fpga | 1 What: /sys/bus/platform/drivers/zynqmp_fpga_manager/firmware:zynqmp-firmware:pcap/status
9 https://docs.xilinx.com/v/u/en-US/ug570-ultrascale-configuration
18 BIT(2) 0: MMCMs/PLLs are not locked
19 1: MMCMs/PLLs are locked
24 BIT(4) 0: Start-up sequence has not finished
25 1: Start-up sequence has finished
27 BIT(5) 0: All I/Os are placed in High-Z state
30 BIT(6) 0: Flip-flops and block RAM are write disabled
31 1: Flip-flops and block RAM are write enabled
54 BIT(17) System Monitor over-temperature if set
[all …]
|
| D | sysfs-bus-iio-frequency-ad9523 | 8 Contact: linux-iio@vger.kernel.org
18 Contact: linux-iio@vger.kernel.org
21 pllY is locked.
25 Contact: linux-iio@vger.kernel.org
29 with their predefined phase offsets (out_altvoltageY_phase).
|
| /kernel/linux/linux-6.6/drivers/iio/frequency/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 # Phase-Locked Loop (PLL) frequency synthesizers
27 # Phase-Locked Loop (PLL) frequency synthesizers
30 menu "Phase-Locked Loop (PLL) frequency synthesizers"
90 Downconverter with integrated Fractional-N PLL and VCO.
|
| /kernel/linux/linux-5.10/mm/ |
| D | mlock.c | 1 // SPDX-License-Identifier: GPL-2.0
41 * in vmscan and, possibly, the fault path; and to support semi-accurate
52 * the mmap_lock for read, and verify that the vma really is locked
67 mod_zone_page_state(page_zone(page), NR_MLOCK, -nr_pages); in clear_page_mlock()
131 * Page must be locked. This is a wrapper for try_to_munlock()
170 * munlock_vma_page - munlock a vma page
174 * HPAGE_PMD_NR - 1 for THP head page)
179 * page locked so that we can leave it on the unevictable lru list and not
202 spin_lock_irq(&pgdat->lru_lock); in munlock_vma_page()
205 /* Potentially, PTE-mapped THP: do not skip the rest PTEs */ in munlock_vma_page()
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/qcom/ |
| D | clk-alpha-pll.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/clk-provider.h>
8 #include "clk-regmap.h"
57 * struct clk_alpha_pll - phase locked loop (PLL)
78 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
81 * @width: width of post-divider
82 * @post_div_shift: shift to differentiate between odd & even post-divider
83 * @post_div_table: table with PLL odd and even post-divider settings
84 * @num_post_div: Number of PLL post-divider settings
|
| D | clk-pll.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
10 #include "clk-regmap.h"
13 * struct pll_freq_tbl - PLL frequency table
28 * struct clk_pll - phase locked loop (PLL)
37 * @hw: handle between common and hardware-specific interfaces
|
| /kernel/linux/linux-5.10/drivers/media/dvb-frontends/ |
| D | tda8261.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
29 const struct tda8261_config *config = state->config; in tda8261_read()
31 struct i2c_msg msg = { .addr = config->addr, .flags = I2C_M_RD,.buf = buf, .len = 1 }; in tda8261_read()
33 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) in tda8261_read()
41 const struct tda8261_config *config = state->config; in tda8261_write()
43 struct i2c_msg msg = { .addr = config->addr, .flags = 0, .buf = buf, .len = 4 }; in tda8261_write()
45 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) in tda8261_write()
53 struct tda8261_state *state = fe->tuner_priv; in tda8261_get_status()
64 pr_debug("%s: Tuner Phase Locked\n", __func__); in tda8261_get_status()
76 struct tda8261_state *state = fe->tuner_priv; in tda8261_get_frequency()
[all …]
|
| D | tda665x.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
27 const struct tda665x_config *config = state->config; in tda665x_read()
29 struct i2c_msg msg = { .addr = config->addr, .flags = I2C_M_RD, .buf = buf, .len = 2 }; in tda665x_read()
31 err = i2c_transfer(state->i2c, &msg, 1); in tda665x_read()
43 const struct tda665x_config *config = state->config; in tda665x_write()
45 struct i2c_msg msg = { .addr = config->addr, .flags = 0, .buf = buf, .len = length }; in tda665x_write()
47 err = i2c_transfer(state->i2c, &msg, 1); in tda665x_write()
59 struct tda665x_state *state = fe->tuner_priv; in tda665x_get_frequency()
61 *frequency = state->frequency; in tda665x_get_frequency()
68 struct tda665x_state *state = fe->tuner_priv; in tda665x_get_status()
[all …]
|
| /kernel/linux/linux-6.6/drivers/media/dvb-frontends/ |
| D | tda8261.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
29 const struct tda8261_config *config = state->config; in tda8261_read()
31 struct i2c_msg msg = { .addr = config->addr, .flags = I2C_M_RD,.buf = buf, .len = 1 }; in tda8261_read()
33 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) in tda8261_read()
41 const struct tda8261_config *config = state->config; in tda8261_write()
43 struct i2c_msg msg = { .addr = config->addr, .flags = 0, .buf = buf, .len = 4 }; in tda8261_write()
45 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) in tda8261_write()
53 struct tda8261_state *state = fe->tuner_priv; in tda8261_get_status()
64 pr_debug("%s: Tuner Phase Locked\n", __func__); in tda8261_get_status()
76 struct tda8261_state *state = fe->tuner_priv; in tda8261_get_frequency()
[all …]
|
| D | tda665x.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
27 const struct tda665x_config *config = state->config; in tda665x_read()
29 struct i2c_msg msg = { .addr = config->addr, .flags = I2C_M_RD, .buf = buf, .len = 2 }; in tda665x_read()
31 err = i2c_transfer(state->i2c, &msg, 1); in tda665x_read()
43 const struct tda665x_config *config = state->config; in tda665x_write()
45 struct i2c_msg msg = { .addr = config->addr, .flags = 0, .buf = buf, .len = length }; in tda665x_write()
47 err = i2c_transfer(state->i2c, &msg, 1); in tda665x_write()
59 struct tda665x_state *state = fe->tuner_priv; in tda665x_get_frequency()
61 *frequency = state->frequency; in tda665x_get_frequency()
68 struct tda665x_state *state = fe->tuner_priv; in tda665x_get_status()
[all …]
|
| /kernel/linux/linux-5.10/include/linux/ |
| D | ww_mutex.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
78 * ww_mutex_init - initialize the w/w mutex
85 * It is not allowed to initialize an already locked mutex.
90 __mutex_init(&lock->base, ww_class->mutex_name, &ww_class->mutex_key); in ww_mutex_init()
91 lock->ctx = NULL; in ww_mutex_init()
93 lock->ww_class = ww_class; in ww_mutex_init()
98 * ww_acquire_init - initialize a w/w acquire context
104 * Context-based w/w mutex acquiring can be done in any order whatsoever within
108 * Mixing of context-based w/w mutex acquiring and single w/w mutex locking can
124 ctx->task = current; in ww_acquire_init()
[all …]
|
| /kernel/linux/linux-6.6/include/linux/ |
| D | ww_mutex.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
35 #define ww_mutex_base_is_locked(b) rt_mutex_base_is_locked(&(b)->rtmutex)
88 * ww_mutex_init - initialize the w/w mutex
96 * It is not allowed to initialize an already locked mutex.
101 ww_mutex_base_init(&lock->base, ww_class->mutex_name, &ww_class->mutex_key); in ww_mutex_init()
102 lock->ctx = NULL; in ww_mutex_init()
104 lock->ww_class = ww_class; in ww_mutex_init()
109 * ww_acquire_init - initialize a w/w acquire context
115 * Context-based w/w mutex acquiring can be done in any order whatsoever within
119 * Mixing of context-based w/w mutex acquiring and single w/w mutex locking can
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/qcom/ |
| D | clk-alpha-pll.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <linux/clk-provider.h>
12 #include "clk-regmap.h"
75 * struct clk_alpha_pll - phase locked loop (PLL)
97 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
100 * @width: width of post-divider
101 * @post_div_shift: shift to differentiate between odd & even post-divider
102 * @post_div_table: table with PLL odd and even post-divider settings
103 * @num_post_div: Number of PLL post-divider settings
|
| D | clk-pll.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
10 #include "clk-regmap.h"
13 * struct pll_freq_tbl - PLL frequency table
28 * struct clk_pll - phase locked loop (PLL)
37 * @hw: handle between common and hardware-specific interfaces
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ti/ |
| D | apll.txt | 3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped APLL with usually two selectable input clocks
7 (reference clock and bypass clock), with analog phase locked
10 modes (locked, low power stop etc.) APLL mostly behaves like
13 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
17 - compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
18 - #clock-cells : from common clock binding; shall be set to 0.
19 - clocks : link phandles of parent clocks (clk-ref and clk-bypass)
20 - reg : address and length of the register set for controlling the APLL.
22 "control" - contains the control register offset
[all …]
|
| D | dpll.txt | 3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped DPLL with usually two selectable input clocks
7 (reference clock and bypass clock), with digital phase locked
10 modes (locked, low power stop etc.) This binding has several
11 sub-types, which effectively result in slightly different setup
14 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
17 - compatible : shall be one of:
18 "ti,omap3-dpll-clock",
19 "ti,omap3-dpll-core-clock",
20 "ti,omap3-dpll-per-clock",
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ti/ |
| D | apll.txt | 3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped APLL with usually two selectable input clocks
7 (reference clock and bypass clock), with analog phase locked
10 modes (locked, low power stop etc.) APLL mostly behaves like
13 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
17 - compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
18 - #clock-cells : from common clock binding; shall be set to 0.
19 - clocks : link phandles of parent clocks (clk-ref and clk-bypass)
20 - reg : address and length of the register set for controlling the APLL.
22 "control" - contains the control register offset
[all …]
|
| D | dpll.txt | 3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped DPLL with usually two selectable input clocks
7 (reference clock and bypass clock), with digital phase locked
10 modes (locked, low power stop etc.) This binding has several
11 sub-types, which effectively result in slightly different setup
14 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
17 - compatible : shall be one of:
18 "ti,omap3-dpll-clock",
19 "ti,omap3-dpll-core-clock",
20 "ti,omap3-dpll-per-clock",
[all …]
|
| /kernel/linux/linux-6.6/arch/arm/mach-ep93xx/ |
| D | hardware.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/arm/mach-ep93xx/include/mach/hardware.h
13 * required high-frequency clocks, the processor uses two phase-locked-
|
| /kernel/linux/linux-5.10/arch/arm/mach-ep93xx/ |
| D | hardware.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/arm/mach-ep93xx/include/mach/hardware.h
13 * required high-frequency clocks, the processor uses two phase-locked-
|
| /kernel/linux/linux-5.10/Documentation/ABI/testing/ |
| D | sysfs-bus-iio-frequency-ad9523 | 8 Contact: linux-iio@vger.kernel.org
18 Contact: linux-iio@vger.kernel.org
21 pllY is locked.
25 Contact: linux-iio@vger.kernel.org
29 with their predefined phase offsets (out_altvoltageY_phase).
|
| /kernel/linux/linux-5.10/sound/soc/tegra/ |
| D | tegra20_spdif.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * tegra20_spdif.h - Definitions for Tegra20 SPDIF driver
6 * Copyright (C) 2011 - NVIDIA, Inc.
9 * Copyright (c) 2008-2009, NVIDIA Corporation
125 * This bit is asserted when the receiver first locked onto the
169 /* B-preamble detection status: 0=not detected, 1=B-preamble detected */
210 * bi-phase period.
215 /* Data strobe mode: 0=Auto-locked 1=Manual locked */
219 * Manual data strobe time within the bi-phase clock period (in terms of
220 * the number of over-sampling clocks).
[all …]
|
| /kernel/linux/linux-6.6/sound/soc/tegra/ |
| D | tegra20_spdif.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * tegra20_spdif.h - Definitions for Tegra20 SPDIF driver
6 * Copyright (C) 2011 - NVIDIA, Inc.
9 * Copyright (c) 2008-2009, NVIDIA Corporation
125 * This bit is asserted when the receiver first locked onto the
169 /* B-preamble detection status: 0=not detected, 1=B-preamble detected */
210 * bi-phase period.
215 /* Data strobe mode: 0=Auto-locked 1=Manual locked */
219 * Manual data strobe time within the bi-phase clock period (in terms of
220 * the number of over-sampling clocks).
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | fsl,imx8qm-lvds-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
15 groups of four data lanes of LVDS data streams. A phase-locked
30 - fsl,imx8qm-lvds-phy
31 - mixel,28fdsoi-lvds-1250-8ch-tx-pll
33 "#phy-cells":
42 power-domains:
[all …]
|