| /kernel/linux/linux-5.10/drivers/clk/hisilicon/ |
| D | clk-hisi-phase.c | 5 * Simple HiSilicon phase clock implementation.
30 static int hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase, in hisi_phase_regval_to_degrees() argument
35 for (i = 0; i < phase->phase_num; i++) in hisi_phase_regval_to_degrees()
36 if (phase->phase_regvals[i] == regval) in hisi_phase_regval_to_degrees()
37 return phase->phase_degrees[i]; in hisi_phase_regval_to_degrees()
44 struct clk_hisi_phase *phase = to_clk_hisi_phase(hw); in hisi_clk_get_phase() local
47 regval = readl(phase->reg); in hisi_clk_get_phase()
48 regval = (regval & phase->mask) >> phase->shift; in hisi_clk_get_phase()
50 return hisi_phase_regval_to_degrees(phase, regval); in hisi_clk_get_phase()
53 static int hisi_phase_degrees_to_regval(struct clk_hisi_phase *phase, in hisi_phase_degrees_to_regval() argument
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/hisilicon/ |
| D | clk-hisi-phase.c | 5 * Simple HiSilicon phase clock implementation.
30 static int hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase, in hisi_phase_regval_to_degrees() argument
35 for (i = 0; i < phase->phase_num; i++) in hisi_phase_regval_to_degrees()
36 if (phase->phase_regvals[i] == regval) in hisi_phase_regval_to_degrees()
37 return phase->phase_degrees[i]; in hisi_phase_regval_to_degrees()
44 struct clk_hisi_phase *phase = to_clk_hisi_phase(hw); in hisi_clk_get_phase() local
47 regval = readl(phase->reg); in hisi_clk_get_phase()
48 regval = (regval & phase->mask) >> phase->shift; in hisi_clk_get_phase()
50 return hisi_phase_regval_to_degrees(phase, regval); in hisi_clk_get_phase()
53 static int hisi_phase_degrees_to_regval(struct clk_hisi_phase *phase, in hisi_phase_degrees_to_regval() argument
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_clock_source.h | 60 SRII(PHASE, DP_DTO, 0),\
61 SRII(PHASE, DP_DTO, 1),\
62 SRII(PHASE, DP_DTO, 2),\
63 SRII(PHASE, DP_DTO, 3),\
64 SRII(PHASE, DP_DTO, 4),\
65 SRII(PHASE, DP_DTO, 5),\
81 SRII(PHASE, DP_DTO, 0),\
82 SRII(PHASE, DP_DTO, 1),\
90 SRII(PHASE, DP_DTO, 0),\
91 SRII(PHASE, DP_DTO, 1),\
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/sunxi-ng/ |
| D | ccu_phase.c | 15 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_get_phase() local
22 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
23 delay = (reg >> phase->shift); in ccu_phase_get_phase()
24 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase()
58 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_set_phase() local
110 spin_lock_irqsave(phase->common.lock, flags); in ccu_phase_set_phase()
111 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_set_phase()
112 reg &= ~GENMASK(phase->width + phase->shift - 1, phase->shift); in ccu_phase_set_phase()
113 writel(reg | (delay << phase->shift), in ccu_phase_set_phase()
114 phase->common.base + phase->common.reg); in ccu_phase_set_phase()
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/sunxi-ng/ |
| D | ccu_phase.c | 15 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_get_phase() local
22 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
23 delay = (reg >> phase->shift); in ccu_phase_get_phase()
24 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase()
58 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_set_phase() local
110 spin_lock_irqsave(phase->common.lock, flags); in ccu_phase_set_phase()
111 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_set_phase()
112 reg &= ~GENMASK(phase->width + phase->shift - 1, phase->shift); in ccu_phase_set_phase()
113 writel(reg | (delay << phase->shift), in ccu_phase_set_phase()
114 phase->common.base + phase->common.reg); in ccu_phase_set_phase()
[all …]
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| /kernel/linux/linux-5.10/Documentation/hwmon/ |
| D | max16601.rst | 64 curr2_input VCORE phase 0 input current.
67 curr3_input VCORE phase 1 input current.
70 curr4_input VCORE phase 2 input current.
73 curr5_input VCORE phase 3 input current.
76 curr6_input VCORE phase 4 input current.
79 curr7_input VCORE phase 5 input current.
82 curr8_input VCORE phase 6 input current.
85 curr9_input VCORE phase 7 input current.
101 curr13_input VCORE phase 0 output current.
104 curr14_input VCORE phase 1 output current.
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_clock_source.h | 60 SRII(PHASE, DP_DTO, 0),\
61 SRII(PHASE, DP_DTO, 1),\
62 SRII(PHASE, DP_DTO, 2),\
63 SRII(PHASE, DP_DTO, 3),\
64 SRII(PHASE, DP_DTO, 4),\
65 SRII(PHASE, DP_DTO, 5),\
81 SRII(PHASE, DP_DTO, 0),\
82 SRII(PHASE, DP_DTO, 1),\
83 SRII(PHASE, DP_DTO, 2),\
84 SRII(PHASE, DP_DTO, 3),\
[all …]
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| /kernel/linux/linux-6.6/drivers/hwmon/pmbus/ |
| D | mp2888.c | 3 * Hardware monitoring driver for MPS Multi-phase Digital VR Controllers
83 * Obtain resolution selector for total and phase current report and protection. in mp2888_current_sense_gain_and_resolution_get()
84 * 0: original resolution; 1: half resolution (in such case phase current value should in mp2888_current_sense_gain_and_resolution_get()
94 mp2888_read_phase(struct i2c_client *client, struct mp2888_data *data, int page, int phase, u8 reg) in mp2888_read_phase() argument
98 ret = pmbus_read_word_data(client, page, phase, reg); in mp2888_read_phase()
102 if (!((phase + 1) % 2)) in mp2888_read_phase()
113 * - Rcs is the internal phase current sense resistor. This parameter depends on hardware in mp2888_read_phase()
116 * If phase current resolution bit is set to 1, READ_CSx value should be doubled. in mp2888_read_phase()
117 * Note, that current phase sensing, providing by the device is not accurate. This is in mp2888_read_phase()
128 mp2888_read_phases(struct i2c_client *client, struct mp2888_data *data, int page, int phase) in mp2888_read_phases() argument
[all …]
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| D | mp2975.c | 3 * Hardware monitoring driver for MPS Multi-phase Digital VR Controllers
130 mp2975_read_word_helper(struct i2c_client *client, int page, int phase, u8 reg, in mp2975_read_word_helper() argument
133 int ret = pmbus_read_word_data(client, page, phase, reg); in mp2975_read_word_helper()
197 int page, int phase, u8 reg) in mp2975_read_phase() argument
201 ret = pmbus_read_word_data(client, page, phase, reg); in mp2975_read_phase()
205 if (!((phase + 1) % MP2975_PAGE_NUM)) in mp2975_read_phase()
216 * - Rcs is the internal phase current sense resistor which is constant in mp2975_read_phase()
222 * Current phase sensing, providing by the device is not accurate in mp2975_read_phase()
225 * case phase current is represented as the maximum between the value in mp2975_read_phase()
228 ret = pmbus_read_word_data(client, page, phase, PMBUS_READ_IOUT); in mp2975_read_phase()
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/sunxi/ |
| D | clk-mod0.c | 173 struct mmc_phase *phase = to_mmc_phase(hw); in mmc_get_phase() local
179 value = readl(phase->reg); in mmc_get_phase()
180 delay = (value >> phase->offset) & 0x3; in mmc_get_phase()
215 struct mmc_phase *phase = to_mmc_phase(hw); in mmc_set_phase() local
266 spin_lock_irqsave(phase->lock, flags); in mmc_set_phase()
267 value = readl(phase->reg); in mmc_set_phase()
268 value &= ~GENMASK(phase->offset + 3, phase->offset); in mmc_set_phase()
269 value |= delay << phase->offset; in mmc_set_phase()
270 writel(value, phase->reg); in mmc_set_phase()
271 spin_unlock_irqrestore(phase->lock, flags); in mmc_set_phase()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/sunxi/ |
| D | clk-mod0.c | 175 struct mmc_phase *phase = to_mmc_phase(hw); in mmc_get_phase() local
181 value = readl(phase->reg); in mmc_get_phase()
182 delay = (value >> phase->offset) & 0x3; in mmc_get_phase()
217 struct mmc_phase *phase = to_mmc_phase(hw); in mmc_set_phase() local
268 spin_lock_irqsave(phase->lock, flags); in mmc_set_phase()
269 value = readl(phase->reg); in mmc_set_phase()
270 value &= ~GENMASK(phase->offset + 3, phase->offset); in mmc_set_phase()
271 value |= delay << phase->offset; in mmc_set_phase()
272 writel(value, phase->reg); in mmc_set_phase()
273 spin_unlock_irqrestore(phase->lock, flags); in mmc_set_phase()
[all …]
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| /kernel/linux/linux-5.10/drivers/mmc/host/ |
| D | sdhci-sirf.c | 77 int phase; in sdhci_sirf_execute_tuning() local
88 phase = 0; in sdhci_sirf_execute_tuning()
92 clock_setting | phase, in sdhci_sirf_execute_tuning()
98 dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n", in sdhci_sirf_execute_tuning()
99 mmc_hostname(mmc), phase); in sdhci_sirf_execute_tuning()
101 start = phase; in sdhci_sirf_execute_tuning()
102 end = phase; in sdhci_sirf_execute_tuning()
104 if (phase == (SIRF_TUNING_COUNT - 1) in sdhci_sirf_execute_tuning()
108 dev_dbg(mmc_dev(mmc), "%s: Found bad phase = %d\n", in sdhci_sirf_execute_tuning()
109 mmc_hostname(mmc), phase); in sdhci_sirf_execute_tuning()
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/meson/ |
| D | clk-phase.c | 11 #include "clk-phase.h"
40 struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); in meson_clk_phase_get_phase() local
43 val = meson_parm_read(clk->map, &phase->ph); in meson_clk_phase_get_phase()
45 return meson_clk_degrees_from_val(val, phase->ph.width); in meson_clk_phase_get_phase()
51 struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); in meson_clk_phase_set_phase() local
54 val = meson_clk_degrees_to_val(degrees, phase->ph.width); in meson_clk_phase_set_phase()
55 meson_parm_write(clk->map, &phase->ph, val); in meson_clk_phase_set_phase()
68 * The phase of mst_sclk clock output can be controlled independently
72 * If necessary, we can still control the phase in the tdm block
87 /* Get phase 0 and sync it to phase 1 and 2 */ in meson_clk_triphase_sync()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/meson/ |
| D | clk-phase.c | 11 #include "clk-phase.h"
40 struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); in meson_clk_phase_get_phase() local
43 val = meson_parm_read(clk->map, &phase->ph); in meson_clk_phase_get_phase()
45 return meson_clk_degrees_from_val(val, phase->ph.width); in meson_clk_phase_get_phase()
51 struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); in meson_clk_phase_set_phase() local
54 val = meson_clk_degrees_to_val(degrees, phase->ph.width); in meson_clk_phase_set_phase()
55 meson_parm_write(clk->map, &phase->ph, val); in meson_clk_phase_set_phase()
68 * The phase of mst_sclk clock output can be controlled independently
72 * If necessary, we can still control the phase in the tdm block
87 /* Get phase 0 and sync it to phase 1 and 2 */ in meson_clk_triphase_sync()
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mmc/ |
| D | samsung,exynos-dw-mshc.yaml | 54 - description: CIU clock phase shift value for tx mode
57 - description: CIU clock phase shift value for rx mode
61 The value of CUI clock phase shift value in transmit mode and CIU clock
62 phase shift value in receive mode for double data rate mode operation.
68 - description: CIU clock phase shift value for tx mode
71 - description: CIU clock phase shift value for rx mode
75 The value of CIU TX and RX clock phase shift value for HS400 mode
78 - valid value for tx phase shift and rx phase shift is 0 to 7.
79 - when CIU clock divider value is set to 3, all possible 8 phase shift
82 phase shift clocks should be 0.
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_dccg.c | 53 int phase; in dccg21_update_dpp_dto() local
57 * program DPP DTO phase and modulo as below in dccg21_update_dpp_dto()
58 * phase = ceiling(dpp_pipe_clk_mhz / 10) in dccg21_update_dpp_dto()
64 * ceiling phase and truncate modulo guarentees the divided in dccg21_update_dpp_dto()
67 phase = (req_dppclk + 9999) / 10000; in dccg21_update_dpp_dto()
69 if (phase > modulo) { in dccg21_update_dpp_dto()
70 /* phase > modulo result in screen corruption in dccg21_update_dpp_dto()
71 * ie phase = 30, mod = 29 for 4k@60 HDMI in dccg21_update_dpp_dto()
74 phase = modulo; in dccg21_update_dpp_dto()
78 * set phase to 10 if dpp isn't used to in dccg21_update_dpp_dto()
[all …]
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| /kernel/linux/linux-5.10/drivers/hwmon/pmbus/ |
| D | mp2975.c | 3 * Hardware monitoring driver for MPS Multi-phase Digital VR Controllers
90 mp2975_read_word_helper(struct i2c_client *client, int page, int phase, u8 reg, in mp2975_read_word_helper() argument
93 int ret = pmbus_read_word_data(client, page, phase, reg); in mp2975_read_word_helper()
122 int page, int phase, u8 reg) in mp2975_read_phase() argument
126 ret = pmbus_read_word_data(client, page, phase, reg); in mp2975_read_phase()
130 if (!((phase + 1) % MP2975_PAGE_NUM)) in mp2975_read_phase()
141 * - Rcs is the internal phase current sense resistor which is constant in mp2975_read_phase()
147 * Current phase sensing, providing by the device is not accurate in mp2975_read_phase()
150 * case phase current is represented as the maximum between the value in mp2975_read_phase()
153 ret = pmbus_read_word_data(client, page, phase, PMBUS_READ_IOUT); in mp2975_read_phase()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/tidss/ |
| D | tidss_dispc_regs.h | 120 #define DISPC_VID_FIR_COEF_H0(phase) (0x6c + (phase) * 4) argument
122 #define DISPC_VID_FIR_COEF_H0_C(phase) (0x90 + (phase) * 4) argument
125 #define DISPC_VID_FIR_COEF_H12(phase) (0xb4 + (phase) * 4) argument
127 #define DISPC_VID_FIR_COEF_H12_C(phase) (0xf4 + (phase) * 4) argument
130 #define DISPC_VID_FIR_COEF_V0(phase) (0x134 + (phase) * 4) argument
132 #define DISPC_VID_FIR_COEF_V0_C(phase) (0x158 + (phase) * 4) argument
135 #define DISPC_VID_FIR_COEF_V12(phase) (0x17c + (phase) * 4) argument
137 #define DISPC_VID_FIR_COEF_V12_C(phase) (0x1bc + (phase) * 4) argument
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| /kernel/linux/linux-6.6/drivers/gpu/drm/tidss/ |
| D | tidss_dispc_regs.h | 120 #define DISPC_VID_FIR_COEF_H0(phase) (0x6c + (phase) * 4) argument
122 #define DISPC_VID_FIR_COEF_H0_C(phase) (0x90 + (phase) * 4) argument
125 #define DISPC_VID_FIR_COEF_H12(phase) (0xb4 + (phase) * 4) argument
127 #define DISPC_VID_FIR_COEF_H12_C(phase) (0xf4 + (phase) * 4) argument
130 #define DISPC_VID_FIR_COEF_V0(phase) (0x134 + (phase) * 4) argument
132 #define DISPC_VID_FIR_COEF_V0_C(phase) (0x158 + (phase) * 4) argument
135 #define DISPC_VID_FIR_COEF_V12(phase) (0x17c + (phase) * 4) argument
137 #define DISPC_VID_FIR_COEF_V12_C(phase) (0x1bc + (phase) * 4) argument
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| /kernel/linux/linux-5.10/drivers/gpu/drm/imx/dcss/ |
| D | dcss-scaler.c | 176 int phase; in dcss_scaler_gaussian_filter() local
181 for (phase = 0; phase < PSC_STORED_PHASES; phase++) { in dcss_scaler_gaussian_filter()
182 coef[phase][0] = 0; in dcss_scaler_gaussian_filter()
183 coef[phase][PSC_NUM_TAPS - 1] = 0; in dcss_scaler_gaussian_filter()
223 /* override phase 0 with identity filter if specified */ in dcss_scaler_gaussian_filter()
230 for (phase = 0; phase < PSC_STORED_PHASES; phase++) { in dcss_scaler_gaussian_filter()
235 sum += coef[phase][i]; in dcss_scaler_gaussian_filter()
237 ll_temp = coef[phase][i]; in dcss_scaler_gaussian_filter()
241 coef[phase][i] = (int)ll_temp; in dcss_scaler_gaussian_filter()
251 * @use_5_taps: 0 for 7 taps per phase, 1 for 5 taps
[all …]
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| /kernel/linux/linux-6.6/drivers/net/wwan/iosm/ |
| D | iosm_ipc_imem_ops.c | 19 ipc_imem_phase_get_string(ipc_imem->phase), if_id); in ipc_imem_sys_wwan_open()
21 /* The network interface is only supported in the runtime phase. */ in ipc_imem_sys_wwan_open()
23 dev_err(ipc_imem->dev, "net:%d : refused phase %s", if_id, in ipc_imem_sys_wwan_open()
24 ipc_imem_phase_get_string(ipc_imem->phase)); in ipc_imem_sys_wwan_open()
66 if (ipc_imem->phase != IPC_P_RUN) { in ipc_imem_sys_wwan_transmit()
67 dev_dbg(ipc_imem->dev, "phase %s transmit", in ipc_imem_sys_wwan_transmit()
68 ipc_imem_phase_get_string(ipc_imem->phase)); in ipc_imem_sys_wwan_transmit()
146 enum ipc_phase phase; in ipc_imem_is_channel_active() local
148 /* Update the current operation phase. */ in ipc_imem_is_channel_active()
149 phase = ipc_imem->phase; in ipc_imem_is_channel_active()
[all …]
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| /kernel/linux/linux-6.6/include/linux/regulator/ |
| D | da9121.h | 3 * DA9121 Single-channel dual-phase 10A buck converter
4 * DA9130 Single-channel dual-phase 10A buck converter (Automotive)
5 * DA9217 Single-channel dual-phase 6A buck converter
6 * DA9122 Dual-channel single-phase 5A buck converter
7 * DA9131 Dual-channel single-phase 5A buck converter (Automotive)
8 * DA9220 Dual-channel single-phase 3A buck converter
9 * DA9132 Dual-channel single-phase 3A buck converter (Automotive)
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | exynos-dw-mshc.txt | 30 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
31 in transmit mode and CIU clock phase shift value in receive mode for single
35 * samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value
36 in transmit mode and CIU clock phase shift value in receive mode for double
39 * samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
45 - First Cell: CIU clock phase shift value for tx mode.
46 - Second Cell: CIU clock phase shift value for rx mode.
49 - valid value for tx phase shift and rx phase shift is 0 to 7.
50 - when CIU clock divider value is set to 3, all possible 8 phase shift
53 phase shift clocks should be 0.
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| D | uncore-power.json | 25 "BriefDescription": "Phase Shed 0 Cycles",
29 "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0",
33 "BriefDescription": "Phase Shed 1 Cycles",
37 "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1",
41 "BriefDescription": "Phase Shed 2 Cycles",
45 "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2",
49 "BriefDescription": "Phase Shed 3 Cycles",
53 "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3",
103 "BriefDescription": "Memory Phase Shedding Cycles",
107 …"PublicDescription": "Memory Phase Shedding Cycles : Counts the number of cycles that the PCU has …
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| /kernel/linux/linux-6.6/drivers/gpu/drm/imx/dcss/ |
| D | dcss-scaler.c | 178 int phase; in dcss_scaler_gaussian_filter() local
183 for (phase = 0; phase < PSC_STORED_PHASES; phase++) { in dcss_scaler_gaussian_filter()
184 coef[phase][0] = 0; in dcss_scaler_gaussian_filter()
185 coef[phase][PSC_NUM_TAPS - 1] = 0; in dcss_scaler_gaussian_filter()
225 /* override phase 0 with identity filter if specified */ in dcss_scaler_gaussian_filter()
232 for (phase = 0; phase < PSC_STORED_PHASES; phase++) { in dcss_scaler_gaussian_filter()
237 sum += coef[phase][i]; in dcss_scaler_gaussian_filter()
239 ll_temp = coef[phase][i]; in dcss_scaler_gaussian_filter()
243 coef[phase][i] = (int)ll_temp; in dcss_scaler_gaussian_filter()
264 * @use_5_taps: 0 for 7 taps per phase, 1 for 5 taps
[all …]
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