| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/rockchip/ |
| D | grf.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/soc/rockchip/grf.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip General Register Files (GRF)
10 - Heiko Stuebner <heiko@sntech.de>
15 - items:
16 - enum:
17 - rockchip,rk3288-sgrf
18 - rockchip,rk3566-pipe-grf
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| /kernel/linux/linux-5.10/drivers/phy/rockchip/ |
| D | phy-rockchip-usb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip usb PHY driver
5 * Copyright (C) 2014 Yunzhi Li <lyz@rock-chips.com>
10 #include <linux/clk-provider.h>
18 #include <linux/phy/phy.h>
56 int (*init_usb_uart)(struct regmap *grf,
74 struct phy *phy; member
80 static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy, in rockchip_usb_phy_power() argument
85 return regmap_write(phy->base->reg_base, phy->reg_offset, val); in rockchip_usb_phy_power()
96 struct rockchip_usb_phy *phy = container_of(hw, in rockchip_usb_phy480m_disable() local
[all …]
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| D | phy-rockchip-dp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip DP PHY driver
6 * Author: Yakir Yang <ykk@@rock-chips.com>
13 #include <linux/phy/phy.h>
28 struct regmap *grf; member
32 static int rockchip_set_phy_state(struct phy *phy, bool enable) in rockchip_set_phy_state() argument
34 struct rockchip_dp_phy *dp = phy_get_drvdata(phy); in rockchip_set_phy_state()
38 ret = regmap_write(dp->grf, GRF_SOC_CON12, in rockchip_set_phy_state()
42 dev_err(dp->dev, "Can't enable PHY power %d\n", ret); in rockchip_set_phy_state()
46 ret = clk_prepare_enable(dp->phy_24m); in rockchip_set_phy_state()
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| D | phy-rockchip-inno-usb2.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Rockchip USB2.0 PHY with Innosilicon IP block driver
9 #include <linux/clk-provider.h>
11 #include <linux/extcon-provider.h>
23 #include <linux/phy/phy.h>
49 * enum usb_chg_state - Different states involved in USB charger detection.
88 * struct rockchip_chg_det_reg - usb charger detect registers
114 * struct rockchip_usb2phy_port_cfg - usb-phy port configuration.
115 * @phy_sus: phy suspend register.
142 * struct rockchip_usb2phy_cfg - usb-phy configuration.
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| /kernel/linux/linux-6.6/drivers/phy/rockchip/ |
| D | phy-rockchip-usb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip usb PHY driver
5 * Copyright (C) 2014 Yunzhi Li <lyz@rock-chips.com>
10 #include <linux/clk-provider.h>
18 #include <linux/phy/phy.h>
56 int (*init_usb_uart)(struct regmap *grf,
74 struct phy *phy; member
80 static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy, in rockchip_usb_phy_power() argument
85 return regmap_write(phy->base->reg_base, phy->reg_offset, val); in rockchip_usb_phy_power()
96 struct rockchip_usb_phy *phy = container_of(hw, in rockchip_usb_phy480m_disable() local
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| D | phy-rockchip-dp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip DP PHY driver
6 * Author: Yakir Yang <ykk@@rock-chips.com>
13 #include <linux/phy/phy.h>
28 struct regmap *grf; member
32 static int rockchip_set_phy_state(struct phy *phy, bool enable) in rockchip_set_phy_state() argument
34 struct rockchip_dp_phy *dp = phy_get_drvdata(phy); in rockchip_set_phy_state()
38 ret = regmap_write(dp->grf, GRF_SOC_CON12, in rockchip_set_phy_state()
42 dev_err(dp->dev, "Can't enable PHY power %d\n", ret); in rockchip_set_phy_state()
46 ret = clk_prepare_enable(dp->phy_24m); in rockchip_set_phy_state()
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| D | phy-rockchip-inno-usb2.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Rockchip USB2.0 PHY with Innosilicon IP block driver
9 #include <linux/clk-provider.h>
11 #include <linux/extcon-provider.h>
23 #include <linux/phy/phy.h>
52 * enum usb_chg_state - Different states involved in USB charger detection.
91 * struct rockchip_chg_det_reg - usb charger detect registers
117 * struct rockchip_usb2phy_port_cfg - usb-phy port configuration.
118 * @phy_sus: phy suspend register.
165 * struct rockchip_usb2phy_cfg - usb-phy configuration.
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | phy-rockchip-naneng-combphy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC Naneng Combo Phy
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3568-naneng-combphy
16 - rockchip,rk3588-naneng-combphy
23 - description: reference clock
24 - description: apb clock
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| D | rockchip-inno-csi-dphy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip-inno-csi-dphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY
10 - Heiko Stuebner <heiko@sntech.de>
13 The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP which
19 - rockchip,px30-csi-dphy
20 - rockchip,rk1808-csi-dphy
21 - rockchip,rk3326-csi-dphy
[all …]
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| D | rockchip-mipi-dphy-rx0.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY
10 - Helen Koike <helen.koike@collabora.com>
11 - Ezequiel Garcia <ezequiel@collabora.com>
14 The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to
19 const: rockchip,rk3399-mipi-dphy-rx0
23 - description: MIPI D-PHY ref clock
[all …]
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| D | phy-rockchip-typec.txt | 1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
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| D | rockchip,pcie3-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip PCIe v3 phy
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3568-pcie3-phy
16 - rockchip,rk3588-pcie3-phy
25 clock-names:
29 data-lanes:
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | rockchip-usb-phy.txt | 1 ROCKCHIP USB2 PHY
4 - compatible: matching the soc type, one of
5 "rockchip,rk3066a-usb-phy"
6 "rockchip,rk3188-usb-phy"
7 "rockchip,rk3288-usb-phy"
8 - #address-cells: should be 1
9 - #size-cells: should be 0
12 - rockchip,grf : phandle to the syscon managing the "general
13 register files" - phy should be a child of the GRF instead
15 Sub-nodes:
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| D | rockchip-mipi-dphy-rx0.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY Device Tree Bindings
10 - Helen Koike <helen.koike@collabora.com>
11 - Ezequiel Garcia <ezequiel@collabora.com>
14 The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to
19 const: rockchip,rk3399-mipi-dphy-rx0
23 - description: MIPI D-PHY ref clock
[all …]
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| D | phy-rockchip-typec.txt | 1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
[all …]
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| /kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac-rk.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
5 * Copyright (C) 2014 Chen-Zhi (Roger Chen)
7 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>
13 #include <linux/phy.h>
65 struct regmap *grf; member
88 struct device *dev = &bsp_priv->pdev->dev; in px30_set_to_rmii()
90 if (IS_ERR(bsp_priv->grf)) { in px30_set_to_rmii()
91 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); in px30_set_to_rmii()
95 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, in px30_set_to_rmii()
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/ |
| D | rockchip,emac.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3036-emac
16 - rockchip,rk3066-emac
17 - rockchip,rk3188-emac
28 - description: host clock
29 - description: reference clock
30 - description: mac TX/RX clock
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/rockchip/ |
| D | dw_hdmi-rockchip.txt | 5 with a companion PHY IP.
9 following device-specific properties.
14 - compatible: should be one of the following:
15 "rockchip,rk3228-dw-hdmi"
16 "rockchip,rk3288-dw-hdmi"
17 "rockchip,rk3328-dw-hdmi"
18 "rockchip,rk3399-dw-hdmi"
19 - reg: See dw_hdmi.txt.
20 - reg-io-width: See dw_hdmi.txt. Shall be 4.
21 - interrupts: HDMI interrupt number
[all …]
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| D | dw_mipi_dsi_rockchip.txt | 5 - #address-cells: Should be <1>.
6 - #size-cells: Should be <0>.
7 - compatible: one of
8 "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"
9 "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"
10 "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"
11 - reg: Represent the physical address range of the controller.
12 - interrupts: Represent the controller's interrupt to the CPU(s).
13 - clocks, clock-names: Phandles to the controller's pll reference
15 For RK3399, a phy config clock (phy_cfg) and a grf clock(grf)
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | emac_rockchip.txt | 4 - compatible: should be "rockchip,<name>-emac"
5 "rockchip,rk3036-emac": found on RK3036 SoCs
6 "rockchip,rk3066-emac": found on RK3066 SoCs
7 "rockchip,rk3188-emac": found on RK3188 SoCs
8 - reg: Address and length of the register set for the device
9 - interrupts: Should contain the EMAC interrupts
10 - rockchip,grf: phandle to the syscon grf used to control speed and mode
12 - phy: see ethernet.txt file in the same directory.
13 - phy-mode: see ethernet.txt file in the same directory.
16 - phy-supply: phandle to a regulator if the PHY needs one
[all …]
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| D | rockchip-dwmac.txt | 6 - compatible: should be "rockchip,<name>-gamc"
7 "rockchip,px30-gmac": found on PX30 SoCs
8 "rockchip,rk3128-gmac": found on RK312x SoCs
9 "rockchip,rk3228-gmac": found on RK322x SoCs
10 "rockchip,rk3288-gmac": found on RK3288 SoCs
11 "rockchip,rk3328-gmac": found on RK3328 SoCs
12 "rockchip,rk3366-gmac": found on RK3366 SoCs
13 "rockchip,rk3368-gmac": found on RK3368 SoCs
14 "rockchip,rk3399-gmac": found on RK3399 SoCs
15 "rockchip,rv1108-gmac": found on RV1108 SoCs
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/rockchip/ |
| D | rockchip,dw-hdmi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Yao <markyao0591@gmail.com>
14 with a companion PHY IP.
17 - $ref: ../bridge/synopsys,dw-hdmi.yaml#
22 - rockchip,rk3228-dw-hdmi
23 - rockchip,rk3288-dw-hdmi
24 - rockchip,rk3328-dw-hdmi
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| D | rockchip,dw-mipi-dsi.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
16 - enum:
17 - rockchip,px30-mipi-dsi
18 - rockchip,rk3288-mipi-dsi
19 - rockchip,rk3399-mipi-dsi
[all …]
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| /kernel/linux/linux-6.6/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac-rk.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
5 * Copyright (C) 2014 Chen-Zhi (Roger Chen)
7 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>
13 #include <linux/phy.h>
82 struct regmap *grf; member
106 struct device *dev = &bsp_priv->pdev->dev; in px30_set_to_rmii()
108 if (IS_ERR(bsp_priv->grf)) { in px30_set_to_rmii()
109 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); in px30_set_to_rmii()
113 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, in px30_set_to_rmii()
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/rockchip/ |
| D | rk3568.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
16 clock-names = "sata", "pmalive", "rxoob";
19 phy-names = "sata-phy";
20 ports-implemented = <0x1>;
21 power-domains = <&power RK3568_PD_PIPE>;
26 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
31 compatible = "rockchip,rk3568-qos", "syscon";
36 compatible = "rockchip,rk3568-qos", "syscon";
41 compatible = "rockchip,rk3568-qos", "syscon";
[all …]
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