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/kernel/linux/linux-6.6/arch/arm64/boot/dts/microchip/
Dsparx5_pcb135_board.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 gpio-restart {
11 compatible = "gpio-restart";
17 compatible = "gpio-leds";
21 default-state = "off";
26 default-state = "off";
31 default-state = "off";
36 default-state = "off";
41 default-state = "off";
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
Dfsl-ls1088a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2017-2020 NXP
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
21 phy-handle = <&mdio2_aquantia_phy>;
22 phy-connection-type = "10gbase-r";
23 pcs-handle = <&pcs2>;
27 phy-handle = <&mdio1_phy5>;
28 phy-connection-type = "qsgmii";
[all …]
Dfsl-ls2088a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 /dts-v1/;
14 #include "fsl-ls2088a.dtsi"
15 #include "fsl-ls208xa-rdb.dtsi"
19 compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
22 stdout-path = "serial1:115200n8";
27 phy-handle = <&mdio1_phy1>;
28 phy-connection-type = "10gbase-r";
32 phy-handle = <&mdio1_phy2>;
33 phy-connection-type = "10gbase-r";
[all …]
Dfsl-lx2160a-bluebox3.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 // Copyright 2020-2021 NXP
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-bluebox3", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
[all …]
Dfsl-ls1088a-ten64.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Based on fsl-ls1088a-rdb.dts
5 * Copyright 2017-2020 NXP
6 * Copyright 2019-2021 Traverse Technologies
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
28 stdout-path = "serial0:115200n8";
32 compatible = "gpio-keys";
[all …]
Dfsl-ls1028a-qds-13bb.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2019-2021 NXP
8 * Requires a SCH-30841 card with lane A of connector rewired to PHY lane C.
9 * Set-up is a SCH-30842 card in slot 1 and SCH-30841 in slot 2.
12 /dts-v1/;
16 #address-cells = <1>;
17 #size-cells = <0>;
19 slot1_sgmii: ethernet-phy@2 {
22 compatible = "ethernet-phy-ieee802.3-c45";
27 phy-handle = <&slot1_sgmii>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/marvell/
Darmada-3720-turris-mox.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/bus/moxtet.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include "armada-372x.dtsi"
16 compatible = "cznic,turris-mox", "marvell,armada3720",
28 stdout-path = "serial0:115200n8";
37 compatible = "gpio-leds";
41 linux,default-trigger = "default-on";
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/marvell/
Darmada-3720-turris-mox.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/bus/moxtet.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include "armada-372x.dtsi"
16 compatible = "cznic,turris-mox", "marvell,armada3720",
28 stdout-path = "serial0:115200n8";
37 compatible = "gpio-leds";
41 linux,default-trigger = "default-on";
[all …]
/kernel/linux/linux-6.6/arch/mips/boot/dts/mscc/
Docelot_pcb120.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/phy/phy-ocelot-serdes.h>
12 compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
15 stdout-path = "serial0:115200n8";
25 phy_int_pins: phy-int-pins {
30 phy_load_save_pins: phy-load-save-pins {
42 pinctrl-names = "default";
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/dsa/
Dmscc,ocelot.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vladimir Oltean <vladimir.oltean@nxp.com>
11 - Claudiu Manoil <claudiu.manoil@nxp.com>
12 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - UNGLinuxDriver@microchip.com
16 There are multiple switches which are either part of the Ocelot-1 family, or
22 Frame DMA or register-based I/O.
26 This is found in the NXP T1040, where it is a memory-mapped platform
[all …]
/kernel/linux/linux-6.6/arch/powerpc/boot/dts/fsl/
Dt1040rdb.dts4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t104xsi-pre.dtsi"
49 fixed-link = <0 1 1000 0 0>;
50 phy-connection-type = "sgmii";
54 fixed-link = <1 1 1000 0 0>;
55 phy-connection-type = "sgmii";
59 phy-handle = <&phy_sgmii_2>;
60 phy-connection-type = "sgmii";
64 phy_sgmii_2: ethernet-phy@3 {
68 /* VSC8514 QSGMII PHY */
[all …]
Dt4240rdb.dts4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "cfi-flash";
67 bank-width = <2>;
68 device-width = <1>;
[all …]
Dt2080qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
66 phy-handle = <&phy_sgmii_s3_1e>;
67 phy-connection-type = "xgmii";
71 phy-handle = <&phy_sgmii_s3_1f>;
72 phy-connection-type = "xgmii";
76 phy-handle = <&rgmii_phy1>;
[all …]
Dt4240qds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 compatible = "cfi-flash";
94 bank-width = <2>;
95 device-width = <1>;
[all …]
Dt2081qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
58 phy-handle = <&phy_sgmii_s7_1c>;
59 phy-connection-type = "sgmii";
63 phy-handle = <&phy_sgmii_s7_1d>;
64 phy-connection-type = "sgmii";
68 phy-handle = <&rgmii_phy1>;
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/
Dt1040rdb.dts4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t104xsi-pre.dtsi"
49 fixed-link = <0 1 1000 0 0>;
50 phy-connection-type = "sgmii";
54 fixed-link = <1 1 1000 0 0>;
55 phy-connection-type = "sgmii";
59 phy-handle = <&phy_sgmii_2>;
60 phy-connection-type = "sgmii";
64 phy_sgmii_2: ethernet-phy@3 {
68 /* VSC8514 QSGMII PHY */
[all …]
Dt4240rdb.dts4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "cfi-flash";
67 bank-width = <2>;
68 device-width = <1>;
[all …]
Dt2080qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
66 phy-handle = <&phy_sgmii_s3_1e>;
67 phy-connection-type = "xgmii";
71 phy-handle = <&phy_sgmii_s3_1f>;
72 phy-connection-type = "xgmii";
76 phy-handle = <&rgmii_phy1>;
[all …]
Dsbc8641d.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
12 /include/ "mpc8641si-pre.dtsi"
35 compatible = "cfi-flash";
37 bank-width = <2>;
38 device-width = <2>;
39 #address-cells = <1>;
40 #size-cells = <1>;
44 read-only;
49 read-only;
58 read-only;
[all …]
Dt4240qds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 compatible = "cfi-flash";
94 bank-width = <2>;
95 device-width = <1>;
[all …]
Dt2081qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
58 phy-handle = <&phy_sgmii_s7_1c>;
59 phy-connection-type = "sgmii";
63 phy-handle = <&phy_sgmii_s7_1d>;
64 phy-connection-type = "sgmii";
68 phy-handle = <&rgmii_phy1>;
[all …]
/kernel/linux/linux-5.10/arch/mips/boot/dts/mscc/
Docelot_pcb120.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/phy/phy-ocelot-serdes.h>
12 compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
15 stdout-path = "serial0:115200n8";
42 pinctrl-names = "default";
43 pinctrl-0 = <&miim1>, <&phy_int_pins>, <&phy_load_save_pins>;
45 phy7: ethernet-phy@0 {
[all …]
/kernel/linux/linux-6.6/drivers/scsi/mpi3mr/
Dmpi3mr_transport.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2017-2023 Broadcom Inc.
6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
13 * mpi3mr_post_transport_req - Issue transport requests and wait
31 * Return: 0 on success, non-zero on failure.
39 mutex_lock(&mrioc->transport_cmds.mutex); in mpi3mr_post_transport_req()
40 if (mrioc->transport_cmds.state & MPI3MR_CMD_PENDING) { in mpi3mr_post_transport_req()
41 retval = -1; in mpi3mr_post_transport_req()
43 mutex_unlock(&mrioc->transport_cmds.mutex); in mpi3mr_post_transport_req()
46 mrioc->transport_cmds.state = MPI3MR_CMD_PENDING; in mpi3mr_post_transport_req()
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/broadcom/
Dbcm958625-meraki-alamo.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
5 * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
8 #include "bcm958625-meraki-mx6x-common.dtsi"
12 compatible = "gpio-keys-polled";
14 poll-interval = <20>;
16 button-reset {
24 compatible = "gpio-leds";
26 led-0 {
27 /* green:wan1-left */
29 function-enumerator = <0>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/microchip/
Dlan966x-pcb8290.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * lan966x-pcb8290.dts - Device Tree file for LAN966X-PCB8290 board
9 /dts-v1/;
11 #include "dt-bindings/phy/phy-lan966x-serdes.h"
15 compatible = "microchip,lan9668-pcb8290", "microchip,lan9668", "microchip,lan966";
17 gpio-restart {
18 compatible = "gpio-restart";
29 miim_a_pins: mdio-pins {
35 pps_out_pins: pps-out-pins {
41 ptp_ext_pins: ptp-ext-pins {
[all …]

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