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Searched +full:phy +full:- +full:input +full:- +full:delay +full:- +full:sd +full:- +full:uhs +full:- +full:ddr50 (Results 1 – 12 of 12) sorted by relevance

/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/
Dcdns,sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
11 - Piotr Sroka <piotrs@cadence.com>
14 - $ref: mmc-controller.yaml
19 - enum:
20 - socionext,uniphier-sd4hc
21 - const: cdns,sd4hc
[all …]
Dsdhci-am654.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/mmc/sdhci-am654.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 - $ref: mmc-controller.yaml#
19 - ti,am654-sdhci-5.1
20 - ti,j721e-sdhci-8bit
21 - ti,j721e-sdhci-4bit
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mmc/
Dcdns,sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
15 - enum:
16 - amd,pensando-elba-sd4hc
17 - microchip,mpfs-sd4hc
18 - socionext,uniphier-sd4hc
19 - const: cdns,sd4hc
[all …]
Dsdhci-am654.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 - $ref: sdhci-common.yaml#
19 - enum:
20 - ti,am62-sdhci
21 - ti,am64-sdhci-4bit
[all …]
/kernel/linux/linux-5.10/drivers/mmc/host/
Dsdhci-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
16 #include "sdhci-pltfm.h"
18 /* HRS - Host Register Set (specific to Cadence) */
19 #define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
38 /* SRS - Slot Register Set (SDHCI-compatible) */
41 /* PHY */
56 * The tuned val register is 6 bit-wide, but not the whole of the range is
57 * available. The range 0-42 seems to be available (then 43 wraps around to 0)
80 { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
81 { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
[all …]
Dsdhci-of-arasan.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
22 #include <linux/phy/phy.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
28 #include "sdhci-cqhci.h"
29 #include "sdhci-pltfm.h"
56 * On some SoCs the syscon area has a feature where the upper 16-bits of
57 * each 32-bit register act as a write mask for the lower 16-bits. This allows
[all …]
/kernel/linux/linux-6.6/drivers/mmc/host/
Dsdhci-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include "sdhci-pltfm.h"
19 /* HRS - Host Register Set (specific to Cadence) */
20 #define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
39 /* SRS - Slot Register Set (SDHCI-compatible) */
42 /* PHY */
57 * The tuned val register is 6 bit-wide, but not the whole of the range is
58 * available. The range 0-42 seems to be available (then 43 wraps around to 0)
90 { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
91 { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
[all …]
Dsdhci-of-arasan.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
23 #include <linux/phy/phy.h>
26 #include <linux/firmware/xlnx-zynqmp.h>
29 #include "sdhci-cqhci.h"
30 #include "sdhci-pltfm.h"
92 * On some SoCs the syscon area has a feature where the upper 16-bits of
93 * each 32-bit register act as a write mask for the lower 16-bits. This allows
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/amlogic/
Dmeson-gx-libretech-pc.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 /* Libretech Amlogic GX PC form factor - AKA: Tartiflette */
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/sound/meson-aiu.h>
14 adc-keys {
15 compatible = "adc-keys";
16 io-channels = <&saradc 0>;
17 io-channel-names = "buttons";
18 keyup-threshold-microvolt = <1800000>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/amlogic/
Dmeson-gx-libretech-pc.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 /* Libretech Amlogic GX PC form factor - AKA: Tartiflette */
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/sound/meson-aiu.h>
14 adc-keys {
15 compatible = "adc-keys";
16 io-channels = <&saradc 0>;
17 io-channel-names = "buttons";
18 keyup-threshold-microvolt = <1800000>;
[all …]
/kernel/linux/patches/linux-5.10/imx8mm_patch/patches/drivers/
D0030_linux_drivers_pci_misc_nvmem_of_mtd_mmc.patch7 Change-Id: Iec160bd007994d82f416debdccfbc0d9bdb40470
9 diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
11 --- a/drivers/misc/Kconfig
13 @@ -314,6 +314,26 @@ config ISL29020
40 diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
42 --- a/drivers/misc/Makefile
44 @@ -19,6 +19,8 @@ obj-$(CONFIG_TIFM_7XX1) += tifm_7xx1.o
45 obj-$(CONFIG_PHANTOM) += phantom.o
46 obj-$(CONFIG_QCOM_COINCELL) += qcom-coincell.o
47 obj-$(CONFIG_QCOM_FASTRPC) += fastrpc.o
[all …]
/kernel/linux/patches/linux-5.10/hispark_taurus_patch/
Dhispark_taurus.patch1 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
3 --- a/arch/arm/Kconfig
5 @@ -322,7 +322,7 @@ config ARCH_MULTIPLATFORM
9 - select AUTO_ZRELADDR
14 @@ -650,6 +650,8 @@ source "arch/arm/mach-highbank/Kconfig"
16 source "arch/arm/mach-hisi/Kconfig"
18 +source "arch/arm/mach-hibvt/Kconfig"
20 source "arch/arm/mach-imx/Kconfig"
22 source "arch/arm/mach-integrator/Kconfig"
23 diff --git a/arch/arm/Makefile b/arch/arm/Makefile
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