| /kernel/linux/linux-6.6/arch/arm64/boot/dts/microchip/ |
| D | sparx5_pcb135_board.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 gpio-restart {
11 compatible = "gpio-restart";
17 compatible = "gpio-leds";
21 default-state = "off";
26 default-state = "off";
31 default-state = "off";
36 default-state = "off";
41 default-state = "off";
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/dsa/ |
| D | mscc,ocelot.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vladimir Oltean <vladimir.oltean@nxp.com>
11 - Claudiu Manoil <claudiu.manoil@nxp.com>
12 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - UNGLinuxDriver@microchip.com
16 There are multiple switches which are either part of the Ocelot-1 family, or
22 Frame DMA or register-based I/O.
26 This is found in the NXP T1040, where it is a memory-mapped platform
[all …]
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| /kernel/linux/linux-5.10/drivers/nfc/s3fwrn5/ |
| D | i2c.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
34 enum s3fwrn5_mode mode; member
40 struct s3fwrn5_i2c_phy *phy = phy_id; in s3fwrn5_i2c_set_wake() local
42 mutex_lock(&phy->mutex); in s3fwrn5_i2c_set_wake()
43 gpio_set_value(phy->gpio_fw_wake, wake); in s3fwrn5_i2c_set_wake()
45 mutex_unlock(&phy->mutex); in s3fwrn5_i2c_set_wake()
48 static void s3fwrn5_i2c_set_mode(void *phy_id, enum s3fwrn5_mode mode) in s3fwrn5_i2c_set_mode() argument
50 struct s3fwrn5_i2c_phy *phy = phy_id; in s3fwrn5_i2c_set_mode() local
52 mutex_lock(&phy->mutex); in s3fwrn5_i2c_set_mode()
54 if (phy->mode == mode) in s3fwrn5_i2c_set_mode()
[all …]
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| /kernel/linux/linux-6.6/drivers/nfc/s3fwrn5/ |
| D | phy_common.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
19 struct phy_common *phy = phy_id; in s3fwrn5_phy_set_wake() local
21 mutex_lock(&phy->mutex); in s3fwrn5_phy_set_wake()
22 gpio_set_value(phy->gpio_fw_wake, wake); in s3fwrn5_phy_set_wake()
25 mutex_unlock(&phy->mutex); in s3fwrn5_phy_set_wake()
29 bool s3fwrn5_phy_power_ctrl(struct phy_common *phy, enum s3fwrn5_mode mode) in s3fwrn5_phy_power_ctrl() argument
31 if (phy->mode == mode) in s3fwrn5_phy_power_ctrl()
34 phy->mode = mode; in s3fwrn5_phy_power_ctrl()
36 gpio_set_value(phy->gpio_en, 1); in s3fwrn5_phy_power_ctrl()
37 gpio_set_value(phy->gpio_fw_wake, 0); in s3fwrn5_phy_power_ctrl()
[all …]
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| /kernel/linux/linux-6.6/drivers/phy/starfive/ |
| D | phy-jh7110-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * StarFive JH7110 PCIe 2.0 PHY driver
15 #include <linux/phy/phy.h>
37 struct phy *phy; member
44 enum phy_mode mode; member
49 if (!data->stg_syscon || !data->sys_syscon) { in phy_usb3_mode_set()
50 dev_err(&data->phy->dev, "doesn't support usb3 mode\n"); in phy_usb3_mode_set()
51 return -EINVAL; in phy_usb3_mode_set()
54 regmap_update_bits(data->stg_syscon, data->stg_pcie_mode, in phy_usb3_mode_set()
56 regmap_update_bits(data->stg_syscon, data->stg_pcie_usb, in phy_usb3_mode_set()
[all …]
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| D | phy-jh7110-usb.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * StarFive JH7110 USB 2.0 PHY driver
14 #include <linux/phy/phy.h>
25 struct phy *phy; member
29 enum phy_mode mode; member
32 static void usb2_set_ls_keepalive(struct jh7110_usb2_phy *phy, bool set) in usb2_set_ls_keepalive() argument
36 /* Host mode enable the LS speed keep-alive signal */ in usb2_set_ls_keepalive()
37 val = readl(phy->regs + USB_LS_KEEPALIVE_OFF); in usb2_set_ls_keepalive()
43 writel(val, phy->regs + USB_LS_KEEPALIVE_OFF); in usb2_set_ls_keepalive()
46 static int usb2_phy_set_mode(struct phy *_phy, in usb2_phy_set_mode()
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/hisilicon/kirin/ |
| D | dw_drm_dsi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2014-2016 HiSilicon Limited.
89 struct mipi_phy_params phy; member
122 static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy) in dsi_calc_phy_rate() argument
152 phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M; in dsi_calc_phy_rate()
153 phy->hstx_ckg_sel = dphy_range_info[i].hstx_ckg_sel; in dsi_calc_phy_rate()
155 if (phy->hstx_ckg_sel <= 7 && in dsi_calc_phy_rate()
156 phy->hstx_ckg_sel >= 4) in dsi_calc_phy_rate()
157 q_pll = 0x10 >> (7 - phy->hstx_ckg_sel); in dsi_calc_phy_rate()
191 phy->pll_fbd_p = 0; in dsi_calc_phy_rate()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/hisilicon/kirin/ |
| D | dw_drm_dsi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2014-2016 Hisilicon Limited.
88 struct mipi_phy_params phy; member
121 static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy) in dsi_calc_phy_rate() argument
151 phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M; in dsi_calc_phy_rate()
152 phy->hstx_ckg_sel = dphy_range_info[i].hstx_ckg_sel; in dsi_calc_phy_rate()
154 if (phy->hstx_ckg_sel <= 7 && in dsi_calc_phy_rate()
155 phy->hstx_ckg_sel >= 4) in dsi_calc_phy_rate()
156 q_pll = 0x10 >> (7 - phy->hstx_ckg_sel); in dsi_calc_phy_rate()
190 phy->pll_fbd_p = 0; in dsi_calc_phy_rate()
[all …]
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| /kernel/linux/linux-5.10/drivers/phy/marvell/ |
| D | phy-mvebu-a3700-comphy.c | 1 // SPDX-License-Identifier: GPL-2.0
9 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
13 #include <linux/arm-smccc.h>
18 #include <linux/phy.h>
19 #include <linux/phy/phy.h>
50 #define COMPHY_FW_MODE(mode) ((mode) << 12) argument
51 #define COMPHY_FW_NET(mode, idx, speed) (COMPHY_FW_MODE(mode) | \ argument
54 #define COMPHY_FW_PCIE(mode, idx, speed, width) (COMPHY_FW_NET(mode, idx, speed) | \ argument
59 enum phy_mode mode; member
68 .mode = _mode, \
[all …]
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| /kernel/linux/linux-5.10/include/linux/phy/ |
| D | phy.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * phy.h -- generic phy header file
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
19 #include <linux/phy/phy-dp.h>
20 #include <linux/phy/phy-mipi-dphy.h>
22 struct phy;
48 * union phy_configure_opts - Opaque generic phy configuration
51 * the MIPI_DPHY phy mode.
61 * struct phy_ops - set of function pointers for performing phy operations
62 * @init: operation to be performed for initializing phy
[all …]
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| /kernel/linux/linux-6.6/include/linux/phy/ |
| D | phy.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * phy.h -- generic phy header file
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
19 #include <linux/phy/phy-dp.h>
20 #include <linux/phy/phy-lvds.h>
21 #include <linux/phy/phy-mipi-dphy.h>
23 struct phy;
55 * union phy_configure_opts - Opaque generic phy configuration
58 * the MIPI_DPHY phy mode.
62 * the LVDS phy mode.
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/ |
| D | fsl-lx2160a-bluebox3.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 // Copyright 2020-2021 NXP
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-bluebox3", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
[all …]
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| /kernel/linux/linux-5.10/drivers/phy/hisilicon/ |
| D | phy-histb-combphy.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016-2017 HiSilicon Co., Ltd. http://www.hisilicon.com
17 #include <linux/phy/phy.h>
20 #include <dt-bindings/phy/phy.h>
48 struct phy *phy; member
49 struct histb_combphy_mode mode; member
55 void __iomem *reg = priv->mmio + COMBPHY_CFG_REG; in nano_register_write()
73 static int is_mode_fixed(struct histb_combphy_mode *mode) in is_mode_fixed() argument
75 return (mode->fixed != PHY_NONE) ? true : false; in is_mode_fixed()
80 struct histb_combphy_mode *mode = &priv->mode; in histb_combphy_set_mode() local
[all …]
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| /kernel/linux/linux-6.6/drivers/phy/hisilicon/ |
| D | phy-histb-combphy.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016-2017 HiSilicon Co., Ltd. http://www.hisilicon.com
17 #include <linux/phy/phy.h>
21 #include <dt-bindings/phy/phy.h>
49 struct phy *phy; member
50 struct histb_combphy_mode mode; member
56 void __iomem *reg = priv->mmio + COMBPHY_CFG_REG; in nano_register_write()
74 static int is_mode_fixed(struct histb_combphy_mode *mode) in is_mode_fixed() argument
76 return (mode->fixed != PHY_NONE) ? true : false; in is_mode_fixed()
81 struct histb_combphy_mode *mode = &priv->mode; in histb_combphy_set_mode() local
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/microchip/ |
| D | lan966x-pcb8290.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * lan966x-pcb8290.dts - Device Tree file for LAN966X-PCB8290 board
9 /dts-v1/;
11 #include "dt-bindings/phy/phy-lan966x-serdes.h"
15 compatible = "microchip,lan9668-pcb8290", "microchip,lan9668", "microchip,lan966";
17 gpio-restart {
18 compatible = "gpio-restart";
29 miim_a_pins: mdio-pins {
35 pps_out_pins: pps-out-pins {
41 ptp_ext_pins: ptp-ext-pins {
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | phy-hi3798cv200-combphy.txt | 1 HiSilicon STB PCIE/SATA/USB3 PHY
4 - compatible: Should be "hisilicon,hi3798cv200-combphy"
5 - reg: Should be the address space for COMBPHY configuration and state
8 - #phy-cells: Should be 1. The cell number is used to select the phy mode
9 as defined in <dt-bindings/phy/phy.h>.
10 - clocks: The phandle to clock provider and clock specifier pair.
11 - resets: The phandle to reset controller and reset specifier pair.
13 Refer to phy/phy-bindings.txt for the generic PHY binding properties.
16 - hisilicon,fixed-mode: If the phy device doesn't support mode select
17 but a fixed mode setting, the property should be present to specify
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | phy-hi3798cv200-combphy.txt | 1 HiSilicon STB PCIE/SATA/USB3 PHY
4 - compatible: Should be "hisilicon,hi3798cv200-combphy"
5 - reg: Should be the address space for COMBPHY configuration and state
8 - #phy-cells: Should be 1. The cell number is used to select the phy mode
9 as defined in <dt-bindings/phy/phy.h>.
10 - clocks: The phandle to clock provider and clock specifier pair.
11 - resets: The phandle to reset controller and reset specifier pair.
13 Refer to phy/phy-bindings.txt for the generic PHY binding properties.
16 - hisilicon,fixed-mode: If the phy device doesn't support mode select
17 but a fixed mode setting, the property should be present to specify
[all …]
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| /kernel/linux/linux-5.10/drivers/phy/ti/ |
| D | phy-ti-pipe3.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-ti-pipe3 - PIPE3 PHY driver.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/phy/phy.h>
19 #include <linux/phy/omap_control_phy.h>
181 enum pipe3_mode mode; member
206 enum pipe3_mode mode; member
212 .mode = PIPE3_MODE_USBSS,
215 /* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */
238 .mode = PIPE3_MODE_SATA,
[all …]
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| /kernel/linux/linux-6.6/drivers/phy/ti/ |
| D | phy-ti-pipe3.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-ti-pipe3 - PIPE3 PHY driver.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/phy/phy.h>
19 #include <linux/phy/omap_control_phy.h>
181 enum pipe3_mode mode; member
206 enum pipe3_mode mode; member
212 .mode = PIPE3_MODE_USBSS,
215 /* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */
238 .mode = PIPE3_MODE_SATA,
[all …]
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| /kernel/linux/linux-5.10/drivers/phy/amlogic/ |
| D | phy-meson-axg-mipi-pcie-analog.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Amlogic AXG MIPI + PCIE analog PHY driver
8 #include <linux/phy/phy.h>
11 #include <dt-bindings/phy/phy.h>
34 #define HHI_MIPI_CNTL2_CH_EN(n) BIT(15 - (n))
38 struct phy *phy; member
39 unsigned int mode; member
50 static int phy_axg_mipi_pcie_analog_power_on(struct phy *phy) in phy_axg_mipi_pcie_analog_power_on() argument
52 struct phy_axg_mipi_pcie_analog_priv *priv = phy_get_drvdata(phy); in phy_axg_mipi_pcie_analog_power_on()
55 if (priv->mode != PHY_TYPE_PCIE) in phy_axg_mipi_pcie_analog_power_on()
[all …]
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| D | phy-meson-gxl-usb2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Meson GXL and GXM USB2 PHY driver
15 #include <linux/phy/phy.h>
18 /* bits [31:27] are read-only */
66 /* bits [31:14] are read-only */
94 enum phy_mode mode; member
107 static int phy_meson_gxl_usb2_init(struct phy *phy) in phy_meson_gxl_usb2_init() argument
109 struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy); in phy_meson_gxl_usb2_init()
112 ret = reset_control_reset(priv->reset); in phy_meson_gxl_usb2_init()
116 ret = clk_prepare_enable(priv->clk); in phy_meson_gxl_usb2_init()
[all …]
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| /kernel/linux/linux-6.6/arch/mips/boot/dts/mscc/ |
| D | ocelot_pcb120.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/phy/phy-ocelot-serdes.h>
12 compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
15 stdout-path = "serial0:115200n8";
25 phy_int_pins: phy-int-pins {
30 phy_load_save_pins: phy-load-save-pins {
42 pinctrl-names = "default";
[all …]
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| /kernel/linux/linux-6.6/drivers/phy/amlogic/ |
| D | phy-meson-gxl-usb2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Meson GXL and GXM USB2 PHY driver
15 #include <linux/phy/phy.h>
18 /* bits [31:27] are read-only */
66 /* bits [31:14] are read-only */
94 enum phy_mode mode; member
107 static int phy_meson_gxl_usb2_init(struct phy *phy) in phy_meson_gxl_usb2_init() argument
109 struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy); in phy_meson_gxl_usb2_init()
112 ret = reset_control_reset(priv->reset); in phy_meson_gxl_usb2_init()
116 ret = clk_prepare_enable(priv->clk); in phy_meson_gxl_usb2_init()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/dsa/ |
| D | mt7530.txt | 6 - compatible: may be compatible = "mediatek,mt7530"
9 - #address-cells: Must be 1.
10 - #size-cells: Must be 0.
11 - mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part
12 on multi-chip module belong to MT7623A has or the remotely standalone
17 - core-supply: Phandle to the regulator node necessary for the core power.
18 - io-supply: Phandle to the regulator node necessary for the I/O power.
19 See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
24 - reset-gpios: Should be a gpio specifier for a reset line.
28 - resets : Phandle pointing to the system reset controller with
[all …]
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| /kernel/linux/linux-6.6/drivers/phy/rockchip/ |
| D | phy-rockchip-snps-pcie3.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Rockchip PCIE3.0 phy driver
16 #include <linux/phy/pcie.h>
17 #include <linux/phy/phy.h>
51 /* mode: RC, EP */
52 int mode; member
58 struct phy *phy; member
69 static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) in rockchip_p3phy_set_mode() argument
71 struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); in rockchip_p3phy_set_mode()
73 /* Actually We don't care EP/RC mode, but just record it */ in rockchip_p3phy_set_mode()
[all …]
|