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/kernel/linux/linux-6.6/include/uapi/linux/
Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
22 #define MDIO_MMD_PHYXS 4 /* PHY Extender Sublayer */
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
40 #define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
41 #define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
42 #define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
49 #define MDIO_PMA_NG_EXTABLE 21 /* 2.5G/5G PMA/PMD extended ability */
51 #define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */
58 /* Media-dependent registers. */
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/kernel/linux/linux-5.10/include/uapi/linux/
Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
22 #define MDIO_MMD_PHYXS 4 /* PHY Extender Sublayer */
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
40 #define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
41 #define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
42 #define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
49 #define MDIO_PMA_NG_EXTABLE 21 /* 2.5G/5G PMA/PMD extended ability */
51 #define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */
57 /* Media-dependent registers. */
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/kernel/linux/linux-5.10/drivers/net/phy/
Dphy-c45.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Clause 45 PHY support
9 #include <linux/phy.h>
12 * genphy_c45_setup_forced - configures a forced speed
20 if (phydev->duplex != DUPLEX_FULL) in genphy_c45_pma_setup_forced()
21 return -EINVAL; in genphy_c45_pma_setup_forced()
33 * PMA/PMD type selection is 1.7.5:0 not 1.7.3:0. See 45.2.1.6.1 in genphy_c45_pma_setup_forced()
34 * in 802.3-2012 and 802.3-2015. in genphy_c45_pma_setup_forced()
38 switch (phydev->speed) { in genphy_c45_pma_setup_forced()
48 /* Assume 1000base-T */ in genphy_c45_pma_setup_forced()
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Dmarvell10g.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Marvell 10G 88x3310 PHY driver
5 * Based upon the ID registers, this PHY appears to be a mixture of IPs
8 * There appears to be several different data paths through the PHY which
9 * are automatically managed by the PHY. The following has been determined
10 * via observation and experimentation for a setup using single-lane Serdes:
12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
18 * XAUI PHYXS -- <appropriate PCS as above>
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dsamsung,ufs-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC series UFS PHY Device Tree Bindings
10 - Alim Akhtar <alim.akhtar@samsung.com>
13 "#phy-cells":
18 - samsung,exynos7-ufs-phy
23 reg-names:
25 - const: phy-pma
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Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
19 power-domains:
24 description: clock-specifier to represent input to the WIZ
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dsamsung,ufs-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC series UFS PHY
10 - Alim Akhtar <alim.akhtar@samsung.com>
13 "#phy-cells":
18 - samsung,exynos7-ufs-phy
19 - samsung,exynosautov9-ufs-phy
20 - tesla,fsd-ufs-phy
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Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
18 - ti,j721s2-wiz-10g
19 - ti,am64-wiz-10g
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Dcdns,dphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/cdns,dphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Pratyush Yadav <pratyush@kernel.org>
15 - cdns,dphy
16 - ti,j721e-dphy
23 - description: PMA state machine clock
24 - description: PLL reference clock
26 clock-names:
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dxlnx,axi-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 provides connectivity to an external ethernet PHY supporting different
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
35 axistream-connected is specified, in which case the reg
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/kernel/linux/linux-6.6/drivers/net/phy/
Dphy-c45.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Clause 45 PHY support
9 #include <linux/phy.h>
11 #include "mdio-open-alliance.h"
14 * genphy_c45_baset1_able - checks if the PMA has BASE-T1 extended abilities
21 if (phydev->pma_extable == -ENODATA) { in genphy_c45_baset1_able()
26 phydev->pma_extable = val; in genphy_c45_baset1_able()
29 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1); in genphy_c45_baset1_able()
33 * genphy_c45_pma_can_sleep - checks if the PMA have sleep support
48 * genphy_c45_pma_resume - wakes up the PMA module
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Dmarvell10g.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Marvell 10G 88x3310 PHY driver
5 * Based upon the ID registers, this PHY appears to be a mixture of IPs
8 * There appears to be several different data paths through the PHY which
9 * are automatically managed by the PHY. The following has been determined
10 * via observation and experimentation for a setup using single-lane Serdes:
12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
18 * XAUI PHYXS -- <appropriate PCS as above>
[all …]
Dmarvell-88q2xxx.c1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell 88Q2XXX automotive 100BASE-T1/1000BASE-T1 PHY driver
7 #include <linux/phy.h>
51 /* Read vendor specific Auto-Negotiation status register to get local in mv88q2xxx_read_link_gbit()
61 * drops can be detected. Do not double-read the status in mv88q2xxx_read_link_gbit()
65 if (!phy_polling_mode(phydev) || !phydev->link) { in mv88q2xxx_read_link_gbit()
82 phydev->link = link; in mv88q2xxx_read_link_gbit()
92 * drops can be detected. Do not double-read the status in mv88q2xxx_read_link_100m()
97 if (!phy_polling_mode(phydev) || !phydev->link) { in mv88q2xxx_read_link_100m()
114 phydev->link = true; in mv88q2xxx_read_link_100m()
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/kernel/linux/linux-6.6/drivers/net/ethernet/sfc/falcon/
Dqt202x_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2012 Solarflare Communications Inc.
15 #include "phy.h"
27 /* Quake-specific MDIO registers */
85 ((1 << PCS_FW_HEARTB_WIDTH) - 1)); in qt2025c_wait_heartbeat()
92 * PHY's on-board EEPROM so it cannot load firmware */ in qt2025c_wait_heartbeat()
93 netif_err(efx, hw, efx->net_dev, in qt2025c_wait_heartbeat()
97 return -ETIMEDOUT; in qt2025c_wait_heartbeat()
116 ((1 << PCS_UC_STATUS_WIDTH) - 1) << PCS_UC_STATUS_LBN) >= in qt2025c_wait_fw_status_good()
120 return -ETIMEDOUT; in qt2025c_wait_fw_status_good()
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Dtxc43128_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2011 Solarflare Communications Inc.
9 * see www.transwitch.com, part is TXC-43128
16 #include "phy.h"
30 * Compile-time config
35 /* Total length of time we'll wait for the PHY to come out of reset (ms) */
52 /* Lane power-down */
56 * initiates a logic reset. Self-clearing */
69 /* Lane power-down */
108 /* Lane power-down */
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/kernel/linux/linux-5.10/drivers/net/ethernet/sfc/falcon/
Dqt202x_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2012 Solarflare Communications Inc.
15 #include "phy.h"
27 /* Quake-specific MDIO registers */
85 ((1 << PCS_FW_HEARTB_WIDTH) - 1)); in qt2025c_wait_heartbeat()
92 * PHY's on-board EEPROM so it cannot load firmware */ in qt2025c_wait_heartbeat()
93 netif_err(efx, hw, efx->net_dev, in qt2025c_wait_heartbeat()
97 return -ETIMEDOUT; in qt2025c_wait_heartbeat()
116 ((1 << PCS_UC_STATUS_WIDTH) - 1) << PCS_UC_STATUS_LBN) >= in qt2025c_wait_fw_status_good()
120 return -ETIMEDOUT; in qt2025c_wait_fw_status_good()
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Dtxc43128_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2011 Solarflare Communications Inc.
9 * see www.transwitch.com, part is TXC-43128
16 #include "phy.h"
30 * Compile-time config
35 /* Total length of time we'll wait for the PHY to come out of reset (ms) */
52 /* Lane power-down */
56 * initiates a logic reset. Self-clearing */
69 /* Lane power-down */
108 /* Lane power-down */
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/kernel/linux/linux-5.10/drivers/phy/cadence/
Dphy-cadence-torrent.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Cadence Torrent SD0801 PHY driver.
9 #include <dt-bindings/phy/phy.h>
20 #include <linux/phy/phy.h>
56 * register offsets from DPTX PHY register block base (i.e MHDP
76 * register offsets from SD0801 PHY register block base (i.e MHDP
161 /* PMA TX Lane registers */
180 /* PMA RX Lane registers */
208 /* PHY PCS common registers */
214 /* PHY PMA common registers */
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/kernel/linux/linux-6.6/drivers/phy/rockchip/
Dphy-rockchip-snps-pcie3.c1 // SPDX-License-Identifier: GPL-2.0
3 * Rockchip PCIE3.0 phy driver
16 #include <linux/phy/pcie.h>
17 #include <linux/phy/phy.h>
58 struct phy *phy; member
69 static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) in rockchip_p3phy_set_mode() argument
71 struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); in rockchip_p3phy_set_mode()
76 priv->mode = PHY_MODE_PCIE_RC; in rockchip_p3phy_set_mode()
79 priv->mode = PHY_MODE_PCIE_EP; in rockchip_p3phy_set_mode()
82 dev_err(&phy->dev, "%s, invalid mode\n", __func__); in rockchip_p3phy_set_mode()
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/kernel/linux/linux-6.6/drivers/phy/cadence/
Dphy-cadence-sierra.c1 // SPDX-License-Identifier: GPL-2.0
3 * Cadence Sierra PHY Driver
10 #include <linux/clk-provider.h>
15 #include <linux/phy/phy.h>
23 #include <dt-bindings/phy/phy.h>
24 #include <dt-bindings/phy/phy-cadence.h>
29 /* PHY register offsets */
203 /* PHY PCS common registers */
209 /* PHY PCS lane registers */
216 /* PHY PMA common registers */
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Dphy-cadence-torrent.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Cadence Torrent SD0801 PHY driver.
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-cadence.h>
12 #include <linux/clk-provider.h>
20 #include <linux/phy/phy.h>
62 * register offsets from DPTX PHY register block base (i.e MHDP
77 * register offsets from SD0801 PHY register block base (i.e MHDP
168 /* PMA TX Lane registers */
189 /* PMA RX Lane registers */
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/bridge/
Dcdns,mhdp8546.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Swapnil Jakhade <sjakhade@cadence.com>
11 - Yuti Amonkar <yamonkar@cadence.com>
16 - cdns,mhdp8546
17 - ti,j721e-mhdp8546
23 - description:
24 Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
25 The AUX and PMA registers are not part of this range, they are instead
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/bridge/
Dcdns,mhdp8546.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Swapnil Jakhade <sjakhade@cadence.com>
11 - Yuti Amonkar <yamonkar@cadence.com>
16 - cdns,mhdp8546
17 - ti,j721e-mhdp8546
22 - description:
23 Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
24 The AUX and PMA registers are not part of this range, they are instead
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/kernel/linux/linux-6.6/drivers/net/ethernet/xilinx/
Dxilinx_axienet.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
147 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
157 #define XAE_PPST_OFFSET 0x00000030 /* PCS PMA Soft Temac Status Reg */
201 /* Transmit inter-frame gap adjustment value */
217 #define XAE_INT_PHYRSTCMPLT_MASK 0x00000100 /* Phy Reset complete */
235 /* In-Band FCS enable (FCS not stripped) */
251 /* In-Band FCS enable (FCS not generated) */
255 /* Inter-frame gap adjustment enable */
277 #define XAE_PHYC_RGMIIHD_MASK 0x00000002 /* RGMII Half-duplex */
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/kernel/linux/linux-6.6/drivers/phy/samsung/
Dphy-samsung-ufs.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * UFS PHY driver for Samsung SoC
18 #include <linux/phy/phy.h>
22 #include "phy-samsung-ufs.h"
24 #define for_each_phy_lane(phy, i) \ argument
25 for (i = 0; i < (phy)->lane_cnt; i++)
27 for (; (cfg)->id; (cfg)++)
31 static void samsung_ufs_phy_config(struct samsung_ufs_phy *phy, in samsung_ufs_phy_config() argument
39 writel(cfg->val, (phy)->reg_pma + cfg->off_0); in samsung_ufs_phy_config()
42 if (cfg->id == PHY_TRSV_BLK) in samsung_ufs_phy_config()
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