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Searched +full:phy +full:- +full:rockchip +full:- +full:typec (Results 1 – 25 of 37) sorted by relevance

12

/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dphy-rockchip-typec.txt1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dphy-rockchip-typec.txt1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
[all …]
/kernel/linux/linux-5.10/drivers/phy/rockchip/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Rockchip platforms
6 tristate "Rockchip Display Port PHY Driver"
10 Enable this to support the Rockchip Display Port PHY.
13 tristate "Rockchip MIPI Synopsys DPHY RX0 driver"
18 Enable this to support the Rockchip MIPI Synopsys DPHY RX0
19 associated to the Rockchip ISP module present in RK3399 SoCs.
22 will be called phy-rockchip-dphy-rx0.
25 tristate "Rockchip EMMC PHY Driver"
29 Enable this to support the Rockchip EMMC PHY.
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o
3 obj-$(CONFIG_PHY_ROCKCHIP_DPHY_RX0) += phy-rockchip-dphy-rx0.o
4 obj-$(CONFIG_PHY_ROCKCHIP_EMMC) += phy-rockchip-emmc.o
5 obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o
6 obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o
7 obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
8 obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
9 obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o
10 obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
/kernel/linux/linux-6.6/drivers/phy/rockchip/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Rockchip platforms
6 tristate "Rockchip Display Port PHY Driver"
10 Enable this to support the Rockchip Display Port PHY.
13 tristate "Rockchip MIPI Synopsys DPHY RX0 driver"
18 Enable this to support the Rockchip MIPI Synopsys DPHY RX0
19 associated to the Rockchip ISP module present in RK3399 SoCs.
22 will be called phy-rockchip-dphy-rx0.
25 tristate "Rockchip EMMC PHY Driver"
29 Enable this to support the Rockchip EMMC PHY.
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o
3 obj-$(CONFIG_PHY_ROCKCHIP_DPHY_RX0) += phy-rockchip-dphy-rx0.o
4 obj-$(CONFIG_PHY_ROCKCHIP_EMMC) += phy-rockchip-emmc.o
5 obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY) += phy-rockchip-inno-csidphy.o
6 obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o
7 obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o
8 obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
9 obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o
10 obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/usb/
Drockchip,dwc3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SuperSpeed DWC3 USB SoC controller
10 - Heiko Stuebner <heiko@sntech.de>
15 Phy documentation is provided in the following places.
17 USB2.0 PHY
18 Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
20 Type-C PHY
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/
Drockchip,dwc3.txt1 Rockchip SuperSpeed DWC3 USB SoC controller
4 - compatible: should contain "rockchip,rk3399-dwc3" for rk3399 SoC
5 - clocks: A list of phandle + clock-specifier pairs for the
6 clocks listed in clock-names
7 - clock-names: Should contain the following:
18 Phy documentation is provided in the following places:
19 Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml - USB2.0 PHY
20 Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt - Type-C PHY
25 compatible = "rockchip,rk3399-dwc3";
28 clock-names = "ref_clk", "suspend_clk",
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/rockchip/
Drk3399-hugsun-x99.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /dts-v1/;
3 #include <dt-bindings/pwm/pwm.h>
4 #include <dt-bindings/input/input.h>
6 #include "rk3399-opp.dtsi"
10 compatible = "hugsun,x99", "rockchip,rk3399";
13 stdout-path = "serial2:1500000n8";
16 clkin_gmac: external-gmac-clock {
17 compatible = "fixed-clock";
18 clock-frequency = <125000000>;
[all …]
Drk3399-roc-pc.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
6 /dts-v1/;
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/pwm/pwm.h>
10 #include "rk3399-opp.dtsi"
13 model = "Firefly ROC-RK3399-PC Board";
14 compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
17 stdout-path = "serial2:1500000n8";
21 compatible = "pwm-backlight";
[all …]
Drk3399-rock-pi-4.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/input/linux-event-codes.h>
9 #include <dt-bindings/pwm/pwm.h>
11 #include "rk3399-opp.dtsi"
15 stdout-path = "serial2:1500000n8";
18 clkin_gmac: external-gmac-clock {
19 compatible = "fixed-clock";
20 clock-frequency = <125000000>;
21 clock-output-names = "clkin_gmac";
[all …]
Drk3399-rockpro64.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/pwm/pwm.h>
10 #include "rk3399-opp.dtsi"
14 stdout-path = "serial2:1500000n8";
17 clkin_gmac: external-gmac-clock {
18 compatible = "fixed-clock";
19 clock-frequency = <125000000>;
20 clock-output-names = "clkin_gmac";
[all …]
Drk3399-nanopi4.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * RK3399-based FriendlyElec boards device tree source
5 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
14 /dts-v1/;
15 #include <dt-bindings/input/linux-event-codes.h>
17 #include "rk3399-opp.dtsi"
21 stdout-path = "serial2:1500000n8";
24 clkin_gmac: external-gmac-clock {
25 compatible = "fixed-clock";
26 clock-frequency = <125000000>;
[all …]
Drk3399-orangepi.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
6 /dts-v1/;
8 #include "dt-bindings/pwm/pwm.h"
9 #include "dt-bindings/input/input.h"
11 #include "rk3399-opp.dtsi"
15 compatible = "rockchip,rk3399-orangepi", "rockchip,rk3399";
18 stdout-path = "serial2:1500000n8";
21 clkin_gmac: external-gmac-clock {
22 compatible = "fixed-clock";
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/rockchip/
Drk3399-hugsun-x99.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /dts-v1/;
3 #include <dt-bindings/pwm/pwm.h>
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/interrupt-controller/irq.h>
7 #include "rk3399-opp.dtsi"
11 compatible = "hugsun,x99", "rockchip,rk3399";
20 stdout-path = "serial2:1500000n8";
23 clkin_gmac: external-gmac-clock {
24 compatible = "fixed-clock";
[all …]
Drk3399-roc-pc.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
6 /dts-v1/;
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/pwm/pwm.h>
10 #include "rk3399-opp.dtsi"
13 model = "Firefly ROC-RK3399-PC Board";
14 compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
22 stdout-path = "serial2:1500000n8";
26 compatible = "pwm-backlight";
[all …]
Drk3399-rock-4c-plus.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
8 /dts-v1/;
9 #include <dt-bindings/leds/common.h>
11 #include "rk3399-t-opp.dtsi"
15 compatible = "radxa,rock-4c-plus", "rockchip,rk3399";
23 stdout-path = "serial2:1500000n8";
26 clkin_gmac: external-gmac-clock {
27 compatible = "fixed-clock";
28 clock-frequency = <125000000>;
[all …]
Drk3568-radxa-e25.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
4 #include "rk3568-radxa-cm3i.dtsi"
8 compatible = "radxa,e25", "radxa,cm3i", "rockchip,rk3568";
14 pwm-leds {
15 compatible = "pwm-leds-multicolor";
17 multi-led {
19 max-brightness = <255>;
21 led-red {
26 led-green {
[all …]
Drk3399-rock-pi-4.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/input/linux-event-codes.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/pwm/pwm.h>
20 stdout-path = "serial2:1500000n8";
23 clkin_gmac: external-gmac-clock {
24 compatible = "fixed-clock";
25 clock-frequency = <125000000>;
26 clock-output-names = "clkin_gmac";
[all …]
Drk3399-eaidk-610.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2022 Fuzhou Rockchip Electronics Co., Ltd.
6 /dts-v1/;
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/pwm/pwm.h>
9 #include <dt-bindings/usb/pd.h>
11 #include "rk3399-opp.dtsi"
14 model = "OPEN AI LAB EAIDK-610";
15 compatible = "openailab,eaidk-610", "rockchip,rk3399";
24 compatible = "pwm-backlight";
[all …]
Drk3399-nanopi4.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * RK3399-based FriendlyElec boards device tree source
5 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
14 /dts-v1/;
15 #include <dt-bindings/input/linux-event-codes.h>
17 #include "rk3399-opp.dtsi"
27 stdout-path = "serial2:1500000n8";
30 clkin_gmac: external-gmac-clock {
31 compatible = "fixed-clock";
32 clock-frequency = <125000000>;
[all …]
Drk3399-firefly.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
6 /dts-v1/;
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/pwm/pwm.h>
10 #include <dt-bindings/usb/pd.h>
12 #include "rk3399-opp.dtsi"
15 model = "Firefly-RK3399 Board";
16 compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
[all …]
Drk3399-rockpro64.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/pwm/pwm.h>
10 #include "rk3399-opp.dtsi"
20 stdout-path = "serial2:1500000n8";
25 compatible = "pwm-backlight";
26 brightness-levels = <0 4 8 16 32 64 128 255>;
27 default-brightness-level = <5>;
32 clkin_gmac: external-gmac-clock {
[all …]
Drk3399-orangepi.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
6 /dts-v1/;
8 #include "dt-bindings/pwm/pwm.h"
9 #include "dt-bindings/input/input.h"
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include "dt-bindings/usb/pd.h"
13 #include "rk3399-opp.dtsi"
17 compatible = "rockchip,rk3399-orangepi", "rockchip,rk3399";
26 stdout-path = "serial2:1500000n8";
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Drockchip-radxa-dalang-carrier.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
8 #include <dt-bindings/pwm/pwm.h>
11 clkin_gmac: external-gmac-clock {
12 compatible = "fixed-clock";
13 clock-frequency = <125000000>;
14 clock-output-names = "clkin_gmac";
15 #clock-cells = <0>;
18 vcc12v_dcin: vcc12v-dcin-regulator {
19 compatible = "regulator-fixed";
[all …]

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