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/kernel/linux/linux-6.6/drivers/usb/phy/
Dphy.c1 // SPDX-License-Identifier: GPL-2.0+
3 * phy.c -- USB phy handling
5 * Copyright (C) 2004-2013 Texas Instruments
15 #include <linux/usb/phy.h>
17 /* Default current range by charger type. */
33 struct usb_phy *phy; member
52 enum usb_phy_type type) in __usb_find_phy() argument
54 struct usb_phy *phy = NULL; in __usb_find_phy() local
56 list_for_each_entry(phy, list, head) { in __usb_find_phy()
57 if (phy->type != type) in __usb_find_phy()
[all …]
/kernel/linux/linux-5.10/drivers/usb/phy/
Dphy.c1 // SPDX-License-Identifier: GPL-2.0+
3 * phy.c -- USB phy handling
5 * Copyright (C) 2004-2013 Texas Instruments
15 #include <linux/usb/phy.h>
17 /* Default current range by charger type. */
33 struct usb_phy *phy; member
46 enum usb_phy_type type) in __usb_find_phy() argument
48 struct usb_phy *phy = NULL; in __usb_find_phy() local
50 list_for_each_entry(phy, list, head) { in __usb_find_phy()
51 if (phy->type != type) in __usb_find_phy()
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
Dfsl-ls2088a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 /dts-v1/;
14 #include "fsl-ls2088a.dtsi"
15 #include "fsl-ls208xa-rdb.dtsi"
19 compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
22 stdout-path = "serial1:115200n8";
27 phy-handle = <&mdio1_phy1>;
28 phy-connection-type = "10gbase-r";
32 phy-handle = <&mdio1_phy2>;
33 phy-connection-type = "10gbase-r";
[all …]
Dfsl-ls1088a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2017-2020 NXP
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
21 phy-handle = <&mdio2_aquantia_phy>;
22 phy-connection-type = "10gbase-r";
23 pcs-handle = <&pcs2>;
27 phy-handle = <&mdio1_phy5>;
28 phy-connection-type = "qsgmii";
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dqcom,usb-hs-phy.txt1 Qualcomm's USB HS PHY
5 - compatible:
7 Value type: <string>
8 Definition: Should contain "qcom,usb-hs-phy" and more specifically one of the
11 "qcom,usb-hs-phy-apq8064"
12 "qcom,usb-hs-phy-msm8916"
13 "qcom,usb-hs-phy-msm8974"
15 - #phy-cells:
17 Value type: <u32>
20 - clocks:
[all …]
Dqcom,usb-hsic-phy.txt1 Qualcomm's USB HSIC PHY
5 - compatible:
7 Value type: <string>
8 Definition: Should contain "qcom,usb-hsic-phy" and more specifically one of the
11 "qcom,usb-hsic-phy-mdm9615"
12 "qcom,usb-hsic-phy-msm8974"
14 - #phy-cells:
16 Value type: <u32>
19 - clocks:
21 Value type: <prop-encoded-array>
[all …]
Dphy-cadence-torrent.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Cadence Torrent SD0801 PHY binding
10 This binding describes the Cadence SD0801 PHY (also known as Torrent PHY)
12 PHY also supports multilink multiprotocol combinations including protocols
16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com>
22 - cdns,torrent-phy
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/usb/
Dsnps,dwc3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 be presented as a standalone DT node with an optional vendor-specific
18 - $ref: usb-drd.yaml#
19 - if:
25 - dr_mode
29 $ref: usb-xhci.yaml#
35 - const: snps,dwc3
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/
Dmarvell,xenon-sdhci.txt7 clock and PHY.
11 - compatible: should be one of the following
12 - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC.
13 Must provide a second register area and marvell,pad-type.
14 - "marvell,armada-ap806-sdhci": For controllers on Armada AP806.
15 - "marvell,armada-cp110-sdhci": For controllers on Armada CP110.
17 - clocks:
22 - clock-names:
27 - reg:
28 * For "marvell,armada-3700-sdhci", two register areas.
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/mediatek/mt76/
Dtestmode.c1 // SPDX-License-Identifier: ISC
8 [MT76_TM_ATTR_RESET] = { .type = NLA_FLAG },
9 [MT76_TM_ATTR_STATE] = { .type = NLA_U8 },
10 [MT76_TM_ATTR_TX_COUNT] = { .type = NLA_U32 },
11 [MT76_TM_ATTR_TX_LENGTH] = { .type = NLA_U32 },
12 [MT76_TM_ATTR_TX_RATE_MODE] = { .type = NLA_U8 },
13 [MT76_TM_ATTR_TX_RATE_NSS] = { .type = NLA_U8 },
14 [MT76_TM_ATTR_TX_RATE_IDX] = { .type = NLA_U8 },
15 [MT76_TM_ATTR_TX_RATE_SGI] = { .type = NLA_U8 },
16 [MT76_TM_ATTR_TX_RATE_LDPC] = { .type = NLA_U8 },
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/kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/
Dt4240rdb.dts4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "cfi-flash";
67 bank-width = <2>;
68 device-width = <1>;
[all …]
Dt2080qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
66 phy-handle = <&phy_sgmii_s3_1e>;
67 phy-connection-type = "xgmii";
71 phy-handle = <&phy_sgmii_s3_1f>;
72 phy-connection-type = "xgmii";
76 phy-handle = <&rgmii_phy1>;
[all …]
Dt4240qds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 compatible = "cfi-flash";
94 bank-width = <2>;
95 device-width = <1>;
[all …]
Dt2081qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
58 phy-handle = <&phy_sgmii_s7_1c>;
59 phy-connection-type = "sgmii";
63 phy-handle = <&phy_sgmii_s7_1d>;
64 phy-connection-type = "sgmii";
68 phy-handle = <&rgmii_phy1>;
[all …]
Dt2080rdb.dts2 * T2080PCIe-RDB Board Device Tree Source
4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
60 phy-handle = <&xg_aq1202_phy3>;
61 phy-connection-type = "xgmii";
65 phy-handle = <&xg_aq1202_phy4>;
66 phy-connection-type = "xgmii";
[all …]
/kernel/linux/linux-6.6/arch/powerpc/boot/dts/fsl/
Dt4240rdb.dts4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "cfi-flash";
67 bank-width = <2>;
68 device-width = <1>;
[all …]
Dt2080qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
66 phy-handle = <&phy_sgmii_s3_1e>;
67 phy-connection-type = "xgmii";
71 phy-handle = <&phy_sgmii_s3_1f>;
72 phy-connection-type = "xgmii";
76 phy-handle = <&rgmii_phy1>;
[all …]
Dt4240qds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 compatible = "cfi-flash";
94 bank-width = <2>;
95 device-width = <1>;
[all …]
Dt2081qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
58 phy-handle = <&phy_sgmii_s7_1c>;
59 phy-connection-type = "sgmii";
63 phy-handle = <&phy_sgmii_s7_1d>;
64 phy-connection-type = "sgmii";
68 phy-handle = <&rgmii_phy1>;
[all …]
Dt2080rdb.dts2 * T2080PCIe-RDB Board Device Tree Source
4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
60 phy-handle = <&xg_aq1202_phy3>;
61 phy-connection-type = "xgmii";
65 phy-handle = <&xg_aq1202_phy4>;
66 phy-connection-type = "xgmii";
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dphy-cadence-torrent.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence Torrent SD0801 PHY
10 This binding describes the Cadence SD0801 PHY (also known as Torrent PHY)
12 PHY also supports multilink multiprotocol combinations including protocols
16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com>
22 - cdns,torrent-phy
[all …]
Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
Dphy-cadence-sierra.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence Sierra PHY
10 This binding describes the Cadence Sierra PHY. Sierra PHY supports multilink
14 - Swapnil Jakhade <sjakhade@cadence.com>
15 - Yuti Amonkar <yamonkar@cadence.com>
20 - cdns,sierra-phy-t0
21 - ti,sierra-phy-t0
[all …]
Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mmc/
Dmarvell,xenon-sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 mmc-controller.yaml and the properties used by the Xenon implementation.
15 sets, clock and PHY.
20 - Ulf Hansson <ulf.hansson@linaro.org>
25 - enum:
26 - marvell,armada-cp110-sdhci
27 - marvell,armada-ap806-sdhci
[all …]

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