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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dnvidia,tegra124-dpaux-padctl.txt1 Device tree binding for NVIDIA Tegra DPAUX pad controller
4 The Tegra Display Port Auxiliary (DPAUX) pad controller manages two pins
8 This document defines the device-specific binding for the DPAUX pad
9 controller. Refer to pinctrl-bindings.txt in this directory for generic
11 the binding document ../display/tegra/nvidia,tegra20-host1x.txt for more
15 -----------
18 from the pinctrl-bindings.txt document.
22 Furthermore, given that the pad functions are only applicable to a
23 single set of pads, the child nodes only need to describe the pad group
27 - groups: Must be "dpaux-io"
[all …]
Dnvidia,tegra210-pinmux.txt4 - compatible: "nvidia,tegra210-pinmux"
5 - reg: Should contain a list of base address and size pairs for:
6 - first entry: The APB_MISC_GP_*_PADCTRL registers (pad control)
7 - second entry: The PINMUX_AUX_* registers (pinmux)
9 Please refer to pinctrl-bindings.txt in this directory for details of the
10 common pinctrl bindings used by client devices, including the meaning of the
13 Tegra's pin configuration nodes act as a container for an arbitrary number of
17 parameters, such as pull-up, tristate, drive strength, etc.
33 include/dt-binding/pinctrl/pinctrl-tegra.h.
35 Required subnode-properties:
[all …]
Dnvidia,tegra194-pinmux.txt4 - compatible: "nvidia,tegra194-pinmux"
5 - reg: Should contain a list of base address and size pairs for:
6 - first entry: The APB_MISC_GP_*_PADCTRL registers (pad control)
7 - second entry: The PINMUX_AUX_* registers (pinmux)
9 Please refer to pinctrl-bindings.txt in this directory for details of the
10 common pinctrl bindings used by client devices, including the meaning of the
13 Tegra's pin configuration nodes act as a container for an arbitrary number of
17 parameters, such as pull-up, tristate, drive strength, etc.
21 include/dt-binding/pinctrl/pinctrl-tegra.h.
23 Required subnode-properties:
[all …]
Dnvidia,tegra124-pinmux.txt3 The Tegra124 pinctrl binding is very similar to the Tegra20 and Tegra30
4 pinctrl binding, as described in nvidia,tegra20-pinmux.txt and
5 nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
9 - compatible: For Tegra124, must contain "nvidia,tegra124-pinmux". For
10 Tegra132, must contain '"nvidia,tegra132-pinmux", "nvidia-tegra124-pinmux"'.
11 - reg: Should contain a list of base address and size pairs for:
12 -- first entry - the drive strength and pad control registers.
13 -- second entry - the pinmux registers
14 -- third entry - the MIPI_PAD_CTRL register
18 include/dt-binding/pinctrl/pinctrl-tegra.h.
[all …]
Dnvidia,tegra114-pinmux.txt3 The Tegra114 pinctrl binding is very similar to the Tegra20 and Tegra30
4 pinctrl binding, as described in nvidia,tegra20-pinmux.txt and
5 nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
9 - compatible: "nvidia,tegra114-pinmux"
10 - reg: Should contain the register physical address and length for each of
11 the pad control and mux registers. The first bank of address must be the
12 driver strength pad control register address and second bank address must
16 - nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
17 - nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
18 - nvidia,lock: Integer. Lock the pin configuration against further changes
[all …]
Dnvidia,tegra30-pinmux.txt3 The Tegra30 pinctrl binding is very similar to the Tegra20 pinctrl binding,
4 as described in nvidia,tegra20-pinmux.txt. In fact, this document assumes
9 - compatible: "nvidia,tegra30-pinmux"
10 - reg: Should contain the register physical address and length for each of
11 the pad control and mux registers.
14 - nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
15 - nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
16 - nvidia,lock: Integer. Lock the pin configuration against further changes
18 - nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
20 As with Tegra20, see the Tegra TRM for complete details regarding which groups
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra186-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Power Management Controller (PMC)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra186-pmc
17 - nvidia,tegra194-pmc
18 - nvidia,tegra234-pmc
[all …]
Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra Power Management Controller (PMC)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra Power Management Controller (PMC)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra20-pmc
18 - nvidia,tegra30-pmc
[all …]
Dnvidia,tegra186-pmc.txt1 NVIDIA Tegra Power Management Controller (PMC)
4 - compatible: Should contain one of the following:
5 - "nvidia,tegra186-pmc": for Tegra186
6 - "nvidia,tegra194-pmc": for Tegra194
7 - "nvidia,tegra234-pmc": for Tegra234
8 - reg: Must contain an (offset, length) pair of the register set for each
9 entry in reg-names.
10 - reg-names: Must include the following entries:
11 - "pmc"
12 - "wake"
[all …]
/kernel/linux/linux-5.10/include/dt-bindings/pinctrl/
Dpinctrl-tegra-io-pad.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * pinctrl-tegra-io-pad.h: Tegra I/O pad source voltage configuration constants
4 * pinctrl bindings.
14 /* Voltage levels of the I/O pad's source rail */
/kernel/linux/linux-6.6/include/dt-bindings/pinctrl/
Dpinctrl-tegra-io-pad.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * pinctrl-tegra-io-pad.h: Tegra I/O pad source voltage configuration constants
4 * pinctrl bindings.
14 /* Voltage levels of the I/O pad's source rail */
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra124-sor.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-sor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra SOR Output Encoder
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
19 pattern: "^sor@[0-9a-f]+$"
23 - enum:
24 - nvidia,tegra124-sor
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/
Dnvidia,tegra210-pinmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra210-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra210-pinmux
19 - description: APB_MISC_GP_*_PADCTRL register (pad control)
20 - description: PINMUX_AUX_* registers (pinmux)
23 "^pinmux(-[a-z0-9-_]+)?$":
[all …]
Dnvidia,tegra124-pinmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra124-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
13 description: The Tegra124 pinctrl binding is very similar to the Tegra20 and
14 Tegra30 pinctrl binding, as described in nvidia,tegra20-pinmux.yaml and
15 nvidia,tegra30-pinmux.yaml. In fact, this document assumes that binding as a
21 - const: nvidia,tegra124-pinmux
[all …]
Dnvidia,tegra30-pinmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra30-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra30-pinmux
19 - description: pad control registers
20 - description: mux registers
23 "^pinmux(-[a-z0-9-_]+)?$":
[all …]
Dnvidia,tegra114-pinmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra114-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra114-pinmux
19 - description: pad control registers
20 - description: mux registers
23 "^pinmux(-[a-z0-9-_]+)?$":
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/nvidia/
Dtegra210.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h>
[all …]
Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
7 #include <dt-bindings/power/tegra194-powergate.h>
8 #include <dt-bindings/reset/tegra194-reset.h>
9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
10 #include <dt-bindings/memory/tegra194-mc.h>
[all …]
Dtegra186.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
[all …]
/kernel/linux/linux-6.6/drivers/mmc/host/
Dsdhci-tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
13 #include <linux/io.h>
20 #include <linux/mmc/slot-gpio.h>
23 #include <linux/pinctrl/consumer.h>
30 #include <soc/tegra/common.h>
32 #include "sdhci-cqhci.h"
33 #include "sdhci-pltfm.h"
36 /* Tegra SDHOST controller vendor register definitions */
114 * 3V3/1V8 pad selection happens through pinctrl state selection depending
[all …]
/kernel/linux/linux-5.10/drivers/mmc/host/
Dsdhci-tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/dma-mapping.h>
14 #include <linux/io.h>
17 #include <linux/pinctrl/consumer.h>
23 #include <linux/mmc/slot-gpio.h>
27 #include "sdhci-cqhci.h"
28 #include "sdhci-pltfm.h"
31 /* Tegra SDHOST controller vendor register definitions */
107 * 3V3/1V8 pad selection happens through pinctrl state selection depending
115 * NVQUIRK_HAS_TMCLK is for SoC's having separate timeout clock for Tegra
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/nvidia/
Dtegra210.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h>
[all …]
Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
[all …]
/kernel/linux/linux-5.10/drivers/soc/tegra/
Dpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/soc/tegra/pmc.c
6 * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
16 #include <linux/clk-provider.h>
18 #include <linux/clk/clk-conf.h>
19 #include <linux/clk/tegra.h>
26 #include <linux/io.h>
36 #include <linux/pinctrl/pinconf-generic.h>
[all …]

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