Searched +full:pinmux +full:- +full:id (Results 1 – 25 of 360) sorted by relevance
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| /kernel/linux/linux-5.10/drivers/pinctrl/zte/ |
| D | pinctrl-zx.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
11 * struct zx_mux_desc - hardware mux descriptor
21 * struct zx_pin_data - hardware per-pin data
23 * @offset: register offset within TOP pinmux controller
24 * @bitpos: bit position within TOP pinmux register
25 * @width: bit width within TOP pinmux register
30 * Unlike TOP pinmux and AON pinconf registers which are arranged pretty
31 * arbitrarily, AON pinmux register bits are well organized per pin id, and
33 * and bit position from pin id. Thus, we only need to define TOP pinmux and
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/ |
| D | loongson,ls2k-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/loongson,ls2k-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-2 SoC Pinctrl Controller
10 - zhanghongchen <zhanghongchen@loongson.cn>
11 - Yinbo Zhu <zhuyinbo@loongson.cn>
14 - $ref: pinctrl.yaml#
18 const: loongson,ls2k-pinctrl
24 '-pins$':
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| D | nvidia,tegra234-pinmux-aon.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra234-pinmux-aon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra234 AON Pinmux Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
13 $ref: nvidia,tegra234-pinmux-common.yaml
17 const: nvidia,tegra234-pinmux-aon
20 "^pinmux(-[a-z0-9-]+)?$":
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| D | brcm,ns-pinmux.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/brcm,ns-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rafał Miłecki <rafal@milecki.pl>
23 - brcm,bcm4708-pinmux
24 - brcm,bcm4709-pinmux
25 - brcm,bcm53012-pinmux
30 reg-names:
34 '-pins$':
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| D | intel,lgm-io.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/intel,lgm-io.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Lightning Mountain SoC pinmux & GPIO controller
10 - Rahul Tanwar <rahul.tanwar@linux.intel.com>
13 Pinmux & GPIO controller controls pin multiplexing & configuration including
18 const: intel,lgm-io
25 '-pins$':
30 $ref: pinmux-node.yaml#
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| D | nvidia,tegra234-pinmux.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra234-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra234 Pinmux Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
13 $ref: nvidia,tegra234-pinmux-common.yaml
17 const: nvidia,tegra234-pinmux
20 "^pinmux(-[a-z0-9-]+)?$":
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| D | nvidia,tegra234-pinmux-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra234-pinmux-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra234 Pinmux Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - description: pinmux registers
19 "^pinmux(-[a-z0-9-]+)?$":
24 $ref: nvidia,tegra-pinmux-common.yaml
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| D | nxp,s32g2-siul2-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/nxp,s32g2-siul2-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ghennadi Procopciuc <Ghennadi.Procopciuc@oss.nxp.com>
12 - Chester Lin <clin@suse.com>
15 S32G2 pinmux is implemented in SIUL2 (System Integration Unit Lite2),
21 IMCR registers need to be revealed for kernel to configure pinmux.
24 MSCR102-MSCR111, MSCR123-MSCR143, IMCR84-IMCR118 and IMCR398-IMCR429.
29 - nxp,s32g2-siul2-pinctrl
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| D | renesas,rzn1-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 - enum:
17 - renesas,r9a06g032-pinctrl # RZ/N1D
18 - renesas,r9a06g033-pinctrl # RZ/N1S
19 - const: renesas,rzn1-pinctrl # Generic RZ/N1
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| D | nvidia,tegra210-pinmux.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra210-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra210 Pinmux Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra210-pinmux
19 - description: APB_MISC_GP_*_PADCTRL register (pad control)
20 - description: PINMUX_AUX_* registers (pinmux)
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| D | pinmux-node.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinmux-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
50 For cases like this, the pin controller driver may use pinctrl-pin-array helper
55 #pinctrl-cells = <2>;
58 pinctrl-pin-array = <
67 Above #pinctrl-cells specifies the number of value cells in addition to the
68 index of the registers. This is similar to the interrupts-extended binding with
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| D | nvidia,tegra124-pinmux.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra124-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra124 Pinmux Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 Tegra30 pinctrl binding, as described in nvidia,tegra20-pinmux.yaml and
15 nvidia,tegra30-pinmux.yaml. In fact, this document assumes that binding as a
21 - const: nvidia,tegra124-pinmux
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| D | mediatek,mt65xx-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@kernel.org>
18 - mediatek,mt2701-pinctrl
19 - mediatek,mt2712-pinctrl
20 - mediatek,mt6397-pinctrl
21 - mediatek,mt7623-pinctrl
22 - mediatek,mt8127-pinctrl
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/mediatek/ |
| D | mt6797.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/clock/mt6797-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/mt6797-pinfunc.h>
14 interrupt-parent = <&sysirq>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <1>;
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| D | mt8365-evk.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2021-2022 BayLibre, SAS.
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/pinctrl/mt8365-pinfunc.h>
19 compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
26 stdout-path = "serial0:921600n8";
31 compatible = "linaro,optee-tz";
36 gpio-keys {
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| D | mt2712-evb.dts | 5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
14 chassis-type = "embedded";
15 compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
27 stdout-path = "serial0:921600n8";
30 cpus_fixed_vproc0: regulator-vproc-buck0 {
31 compatible = "regulator-fixed";
32 regulator-name = "vproc_buck0";
33 regulator-min-microvolt = <1000000>;
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/mediatek/ |
| D | mt6797.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/clock/mt6797-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/mt6797-pinfunc.h>
14 interrupt-parent = <&sysirq>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <1>;
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| D | mt2712-evb.dts | 5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
14 compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
26 stdout-path = "serial0:921600n8";
29 cpus_fixed_vproc0: regulator-vproc-buck0 {
30 compatible = "regulator-fixed";
31 regulator-name = "vproc_buck0";
32 regulator-min-microvolt = <1000000>;
33 regulator-max-microvolt = <1000000>;
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| /kernel/linux/linux-6.6/arch/riscv/boot/dts/starfive/ |
| D | jh7110-starfive-visionfive-2.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
9 #include "jh7110-pinfunc.h"
10 #include <dt-bindings/gpio/gpio.h>
26 stdout-path = "serial0:115200n8";
30 timebase-frequency = <4000000>;
38 gpio-restart {
39 compatible = "gpio-restart";
46 clock-frequency = <74250000>;
50 clock-frequency = <125000000>;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | intel,lgm-io.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/intel,lgm-io.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Lightning Mountain SoC pinmux & GPIO controller binding
10 - Rahul Tanwar <rahul.tanwar@linux.intel.com>
13 Pinmux & GPIO controller controls pin multiplexing & configuration including
18 const: intel,lgm-io
25 '-pins$':
30 $ref: pinmux-node.yaml#
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| D | renesas,rzn1-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gareth Williams <gareth.williams.jx@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 - enum:
17 - renesas,r9a06g032-pinctrl # RZ/N1D
18 - renesas,r9a06g033-pinctrl # RZ/N1S
19 - const: renesas,rzn1-pinctrl # Generic RZ/N1
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| D | pinmux-node.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinmux-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
50 For cases like this, the pin controller driver may use pinctrl-pin-array helper
55 #pinctrl-cells = <2>;
58 pinctrl-pin-array = <
67 Above #pinctrl-cells specifies the number of value cells in addition to the
68 index of the registers. This is similar to the interrupts-extended binding with
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/ti/omap/ |
| D | omap4-epson-embt2ws.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
5 /dts-v1/;
7 #include <dt-bindings/input/input.h>
11 model = "Epson Moverio BT-200";
19 backlight-left {
20 compatible = "pwm-backlight";
22 power-supply = <&unknown_supply>;
25 backlight-right {
26 compatible = "pwm-backlight";
28 power-supply = <&unknown_supply>;
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/microchip/ |
| D | at91-kizbox3-hs.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * at91-kizbox3-hs.dts - Device Tree file for Overkiz KIZBOX3-HS board
11 /dts-v1/;
12 #include "at91-kizbox3_common.dtsi"
15 model = "Overkiz KIZBOX3-HS";
16 compatible = "overkiz,kizbox3-hs", "atmel,sama5d2", "atmel,sama5";
18 led-controller-1 {
21 led-1 {
25 led-2 {
29 led-3 {
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | at91-kizbox3-hs.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * at91-kizbox3-hs.dts - Device Tree file for Overkiz KIZBOX3-HS board
11 /dts-v1/;
12 #include "at91-kizbox3_common.dtsi"
15 model = "Overkiz KIZBOX3-HS";
16 compatible = "overkiz,kizbox3-hs", "atmel,sama5d2", "atmel,sama5";
39 compatible = "gpio-leds";
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_led_red
48 default-state = "off";
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