| /kernel/linux/linux-5.10/drivers/clk/qcom/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
17 #include "clk-pll.h"
26 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
35 /* Skip if already enabled or in FSM mode */ in clk_pll_enable()
39 /* Disable PLL bypass mode. */ in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
47 * de-asserting the reset. Delay 10us just to be safe. in clk_pll_enable()
51 /* De-assert active-low PLL reset. */ in clk_pll_enable()
[all …]
|
| D | clk-alpha-pll.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
12 #include "clk-alpha-pll.h"
15 #define PLL_MODE(p) ((p)->offset + 0x0)
34 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
35 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
36 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
37 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
39 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
41 # define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0)
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/qcom/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
17 #include "clk-pll.h"
26 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
35 /* Skip if already enabled or in FSM mode */ in clk_pll_enable()
39 /* Disable PLL bypass mode. */ in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
47 * de-asserting the reset. Delay 10us just to be safe. in clk_pll_enable()
51 /* De-assert active-low PLL reset. */ in clk_pll_enable()
[all …]
|
| D | clk-alpha-pll.c | 1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk-provider.h>
13 #include "clk-alpha-pll.h"
16 #define PLL_MODE(p) ((p)->offset + 0x0)
36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
38 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
39 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
41 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
43 # define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0)
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/spear/ |
| D | clk-vco-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * VCO-PLL clock implementation
9 #define pr_fmt(fmt) "clk-vco-pll: " fmt
11 #include <linux/clk-provider.h>
18 * DOC: VCO-PLL clock
20 * VCO and PLL rate are derived from following equations:
22 * In normal mode
25 * In Dithered mode
28 * pll_rate = pll/2^p
30 * vco and pll are very closely bound to each other, "vco needs to program:
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/spear/ |
| D | clk-vco-pll.c | 9 * VCO-PLL clock implementation
12 #define pr_fmt(fmt) "clk-vco-pll: " fmt
14 #include <linux/clk-provider.h>
21 * DOC: VCO-PLL clock
23 * VCO and PLL rate are derived from following equations:
25 * In normal mode
28 * In Dithered mode
31 * pll_rate = pll/2^p
33 * vco and pll are very closely bound to each other, "vco needs to program:
34 * mode, m & n" and "pll needs to program p", both share common enable/disable
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/nuvoton/ |
| D | clk-ma35d1-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Chi-Fang Li <cfli0@nuvoton.com>
8 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
18 #include "clk-ma35d1.h"
20 /* PLL frequency limits */
36 /* bit fields for REG_CLK_PLL0CTL0, which is SMIC PLL design */
70 u8 mode; member
99 static unsigned long ma35d1_calc_pll_freq(u8 mode, u32 *reg_ctl, unsigned long parent_rate) in ma35d1_calc_pll_freq() argument
111 if (mode == PLL_MODE_INT) { in ma35d1_calc_pll_freq()
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/starfive/ |
| D | clk-starfive-jh7110-pll.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * StarFive JH7110 PLL Clock Generator Driver
8 * This driver is about to register JH7110 PLL clock generator and support ops.
9 * The JH7110 have three PLL clock, PLL0, PLL1 and PLL2.
10 * Each PLL clocks work in integer mode or fraction mode by some dividers,
17 * M: frequency dividing ratio of pre-divider, set by prediv[5:0].
22 #include <linux/clk-provider.h>
30 #include <dt-bindings/clock/starfive,jh7110-crg.h>
86 unsigned mode : 1; member
143 struct jh7110_pll_data pll[JH7110_PLLCLK_END]; member
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/zynqmp/ |
| D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC PLL driver
5 * Copyright (C) 2016-2018 Xilinx
9 #include <linux/clk-provider.h>
11 #include "clk-zynqmp.h"
14 * struct zynqmp_pll - PLL clock
15 * @hw: Handle between common and hardware-specific interfaces
16 * @clk_id: PLL clock ID
44 * zynqmp_pll_get_mode() - Get mode of PLL
45 * @hw: Handle between common and hardware-specific interfaces
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/zynqmp/ |
| D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC PLL driver
5 * Copyright (C) 2016-2018 Xilinx
9 #include <linux/clk-provider.h>
11 #include "clk-zynqmp.h"
14 * struct zynqmp_pll - PLL clock
15 * @hw: Handle between common and hardware-specific interfaces
16 * @clk_id: PLL clock ID
43 * zynqmp_pll_get_mode() - Get mode of PLL
44 * @hw: Handle between common and hardware-specific interfaces
[all …]
|
| /kernel/linux/linux-5.10/drivers/video/fbdev/aty/ |
| D | radeon_base.c | 38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
239 /* these common regs are cleared before mode setting so they do not
262 static int default_dynclk = -2;
282 if (rinfo->no_schedule || oops_in_progress) in _radeon_msleep()
290 /* Called if (rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS) is set */ in radeon_pll_errata_after_index_slow()
297 if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) { in radeon_pll_errata_after_data_slow()
301 if (rinfo->errata & CHIP_ERRATA_R300_CG) { in radeon_pll_errata_after_data_slow()
316 spin_lock_irqsave(&rinfo->reg_lock, flags); in _OUTREGP()
321 spin_unlock_irqrestore(&rinfo->reg_lock, flags); in _OUTREGP()
409 if (!rinfo->bios_seg) in radeon_unmap_ROM()
[all …]
|
| /kernel/linux/linux-6.6/drivers/video/fbdev/aty/ |
| D | radeon_base.c | 38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
240 /* these common regs are cleared before mode setting so they do not
263 static int default_dynclk = -2;
283 if (rinfo->no_schedule || oops_in_progress) in _radeon_msleep()
291 /* Called if (rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS) is set */ in radeon_pll_errata_after_index_slow()
298 if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) { in radeon_pll_errata_after_data_slow()
302 if (rinfo->errata & CHIP_ERRATA_R300_CG) { in radeon_pll_errata_after_data_slow()
317 spin_lock_irqsave(&rinfo->reg_lock, flags); in _OUTREGP()
322 spin_unlock_irqrestore(&rinfo->reg_lock, flags); in _OUTREGP()
410 if (!rinfo->bios_seg) in radeon_unmap_ROM()
[all …]
|
| /kernel/linux/linux-6.6/arch/arm64/boot/dts/qcom/ |
| D | sa8295p-adp.dts | 1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
11 #include <dt-bindings/spmi/spmi.h>
14 #include "sa8540p-pmics.dtsi"
18 compatible = "qcom,sa8295p-adp", "qcom,sa8540p";
25 stdout-path = "serial0:115200n8";
28 dp2-connector {
29 compatible = "dp-connector";
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/rcar-du/ |
| D | rcar_lvds.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * rcar_lvds.c -- R-Car LVDS Encoder
5 * Copyright (C) 2013-2018 Renesas Electronics Corporation
50 #define RCAR_LVDS_QUIRK_EXT_PLL BIT(3) /* Has extended PLL */
51 #define RCAR_LVDS_QUIRK_DUAL_LINK BIT(4) /* Supports dual-link operation */
88 iowrite32(data, lvds->mmio + reg); in rcar_lvds_write()
91 /* -----------------------------------------------------------------------------
99 return drm_panel_get_modes(lvds->panel, connector); in rcar_lvds_connector_get_modes()
111 if (!conn_state->crtc) in rcar_lvds_connector_atomic_check()
114 if (list_empty(&connector->modes)) { in rcar_lvds_connector_atomic_check()
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/bcm/ |
| D | clk-iproc-armpll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
66 static unsigned int __get_fid(struct iproc_arm_pll *pll) in __get_fid() argument
71 val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET); in __get_fid()
80 val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET); in __get_fid()
84 val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET); in __get_fid()
88 pr_debug("%s: fid override %u->%u\n", __func__, fid, in __get_fid()
101 * - 25 MHz Crystal
102 * - System clock
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/i2c/ |
| D | adv7343.txt | 3 The ADV7343 are high speed, digital-to-analog video encoders in a 64-lead LQFP
4 package. Six high speed, 3.3 V, 11-bit video DACs provide support for composite
5 (CVBS), S-Video (Y-C), and component (YPrPb/RGB) analog outputs in standard
10 - compatible: Must be "adi,adv7343"
13 - adi,power-mode-sleep-mode: on enable the current consumption is reduced to
14 micro ampere level. All DACs and the internal PLL
16 - adi,power-mode-pll-ctrl: PLL and oversampling control. This control allows
17 internal PLL 1 circuit to be powered down and the
19 - ad,adv7343-power-mode-dac: array configuring the power on/off DAC's 1..6,
22 - ad,adv7343-sd-config-dac-out: array configure SD DAC Output's 1 and 2, 0 = OFF
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/i2c/ |
| D | adv7343.txt | 3 The ADV7343 are high speed, digital-to-analog video encoders in a 64-lead LQFP
4 package. Six high speed, 3.3 V, 11-bit video DACs provide support for composite
5 (CVBS), S-Video (Y-C), and component (YPrPb/RGB) analog outputs in standard
10 - compatible: Must be "adi,adv7343"
13 - adi,power-mode-sleep-mode: on enable the current consumption is reduced to
14 micro ampere level. All DACs and the internal PLL
16 - adi,power-mode-pll-ctrl: PLL and oversampling control. This control allows
17 internal PLL 1 circuit to be powered down and the
19 - ad,adv7343-power-mode-dac: array configuring the power on/off DAC's 1..6,
22 - ad,adv7343-sd-config-dac-out: array configure SD DAC Output's 1 and 2, 0 = OFF
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/bcm/ |
| D | clk-iproc-armpll.c | 17 #include <linux/clk-provider.h>
23 #include "clk-iproc.h"
76 static unsigned int __get_fid(struct iproc_arm_pll *pll) in __get_fid() argument
81 val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET); in __get_fid()
90 val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET); in __get_fid()
94 val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET); in __get_fid()
98 pr_debug("%s: fid override %u->%u\n", __func__, fid, in __get_fid()
111 * - 25 MHz Crystal
112 * - System clock
113 * - PLL channel 0 (slow clock)
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | silabs,si5341.txt | 6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
13 clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
20 The driver can be used in "as is" mode, reading the current settings from the
21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
27 The driver currently only supports XTAL input mode, and does not support any
34 - compatible: shall be one of the following:
35 "silabs,si5340" - Si5340 A/B/C/D
36 "silabs,si5341" - Si5341 A/B/C/D
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | silabs,si5341.txt | 6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
13 clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
20 The driver can be used in "as is" mode, reading the current settings from the
21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
33 - compatible: shall be one of the following:
34 "silabs,si5340" - Si5340 A/B/C/D
35 "silabs,si5341" - Si5341 A/B/C/D
36 "silabs,si5342" - Si5342 A/B/C/D
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
| D | atombios_crtc.c | 2 * Copyright 2007-8 Advanced Micro Devices, Inc.
36 #include "atom-bits.h"
39 struct drm_display_mode *mode, in atombios_overscan_setup() argument
42 struct drm_device *dev = crtc->dev; in atombios_overscan_setup()
43 struct radeon_device *rdev = dev->dev_private; in atombios_overscan_setup()
51 args.ucCRTC = radeon_crtc->crtc_id; in atombios_overscan_setup()
53 switch (radeon_crtc->rmx_type) { in atombios_overscan_setup()
55 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in atombios_overscan_setup()
56 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in atombios_overscan_setup()
57 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in atombios_overscan_setup()
[all …]
|
| D | radeon_display.c | 2 * Copyright 2007-8 Advanced Micro Devices, Inc.
55 struct drm_device *dev = crtc->dev; in avivo_crtc_load_lut()
56 struct radeon_device *rdev = dev->dev_private; in avivo_crtc_load_lut()
60 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); in avivo_crtc_load_lut()
61 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
63 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
64 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
65 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
67 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut()
68 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut()
[all …]
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/radeon/ |
| D | atombios_crtc.c | 2 * Copyright 2007-8 Advanced Micro Devices, Inc.
36 #include "atom-bits.h"
39 struct drm_display_mode *mode, in atombios_overscan_setup() argument
42 struct drm_device *dev = crtc->dev; in atombios_overscan_setup()
43 struct radeon_device *rdev = dev->dev_private; in atombios_overscan_setup()
51 args.ucCRTC = radeon_crtc->crtc_id; in atombios_overscan_setup()
53 switch (radeon_crtc->rmx_type) { in atombios_overscan_setup()
55 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in atombios_overscan_setup()
56 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in atombios_overscan_setup()
57 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in atombios_overscan_setup()
[all …]
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/stm/ |
| D | dw_mipi_dsi-stm.c | 1 // SPDX-License-Identifier: GPL-2.0
32 #define WCFGR_DSIM BIT(0) /* DSI Mode */
39 #define WISR_PLLLS BIT(8) /* PLL Lock Status */
46 #define DSI_WRPCR 0x0430 /* Wrapper Regulator & Pll Ctrl Reg */
47 #define WRPCR_PLLEN BIT(0) /* PLL ENable */
48 #define WRPCR_NDIV GENMASK(8, 2) /* pll loop DIVision Factor */
49 #define WRPCR_IDF GENMASK(14, 11) /* pll Input Division Factor */
50 #define WRPCR_ODF GENMASK(17, 16) /* pll Output Division Factor */
73 /* Sleep & timeout for regulator on/off, pll lock/unlock & fifo empty */
89 writel(val, dsi->base + reg); in dsi_write()
[all …]
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/renesas/rcar-du/ |
| D | rcar_lvds.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car LVDS Encoder
5 * Copyright (C) 2013-2018 Renesas Electronics Corporation
13 #include <linux/media-bus-format.h>
53 #define RCAR_LVDS_QUIRK_EXT_PLL BIT(3) /* Has extended PLL */
54 #define RCAR_LVDS_QUIRK_DUAL_LINK BIT(4) /* Supports dual-link operation */
88 return ioread32(lvds->mmio + reg); in rcar_lvds_read()
93 iowrite32(data, lvds->mmio + reg); in rcar_lvds_write()
96 /* -----------------------------------------------------------------------------
97 * PLL Setup
[all …]
|