| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | allwinner,sun4i-a10-pll5-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll5-clk.yaml#
23 const: allwinner,sun4i-a10-pll5-clk
47 compatible = "allwinner,sun4i-a10-pll5-clk";
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| D | allwinner,sun4i-a10-mbus-clk.yaml | 50 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
59 clocks = <&osc24M>, <&pll6 1>, <&pll5>;
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| D | allwinner,sun4i-a10-display-clk.yaml | 53 clocks = <&pll3>, <&pll7>, <&pll5 1>;
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| D | allwinner,sun4i-a10-mmc-clk.yaml | 71 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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| D | allwinner,sun4i-a10-mod0-clk.yaml | 67 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | allwinner,sun4i-a10-pll5-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll5-clk.yaml#
23 const: allwinner,sun4i-a10-pll5-clk
47 compatible = "allwinner,sun4i-a10-pll5-clk";
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| D | allwinner,sun4i-a10-mbus-clk.yaml | 50 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
59 clocks = <&osc24M>, <&pll6 1>, <&pll5>;
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| D | allwinner,sun4i-a10-display-clk.yaml | 53 clocks = <&pll3>, <&pll7>, <&pll5 1>;
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| D | allwinner,sun4i-a10-mmc-clk.yaml | 71 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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| D | allwinner,sun4i-a10-mod0-clk.yaml | 67 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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| /kernel/linux/linux-5.10/drivers/clk/renesas/ |
| D | r8a779a0-cpg-mssr.c | 101 DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_R8A779A0_PLL5, CLK_MAIN),
231 * MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC
243 /* EXTAL div PLL1 mult/div PLL5 mult/div OSC prediv */
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| /kernel/linux/linux-6.6/drivers/clk/renesas/ |
| D | r8a779f0-cpg-mssr.c | 64 DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
179 * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
191 …/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div O…
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| D | r8a779a0-cpg-mssr.c | 72 DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
246 * MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC
257 …/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div O…
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| D | r8a779g0-cpg-mssr.c | 74 DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
247 * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
259 …/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div O…
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| D | rzg2l-cpg.c | 120 * @mux_dsi_div_params: pll5 mux and dsi div parameters
654 * OSC --> PLL5 --> FOUTPOSTDIV-->| in rzg2l_cpg_sipll5_set_rate()
659 * rate and the pll5 parameters for generating FOUTPOSTDIV. It propagates in rzg2l_cpg_sipll5_set_rate()
662 * OSC --> PLL5 --> FOUTPOSTDIV in rzg2l_cpg_sipll5_set_rate()
672 /* Put PLL5 into standby mode */ in rzg2l_cpg_sipll5_set_rate()
677 dev_err(priv->dev, "failed to release pll5 lock"); in rzg2l_cpg_sipll5_set_rate()
704 dev_err(priv->dev, "failed to lock pll5"); in rzg2l_cpg_sipll5_set_rate()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mips/ |
| D | mscc.txt | 48 configuration and status of PLL5, RCOMP, SyncE, SerDes configurations and
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mips/ |
| D | mscc.txt | 48 configuration and status of PLL5, RCOMP, SyncE, SerDes configurations and
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| /kernel/linux/linux-5.10/drivers/clk/mmp/ |
| D | clk-of-pxa1928.c | 41 {0, "pll5", NULL, 0, 1248000000},
146 static const char *sdh_parent_names[] = {"pll1_624", "pll5p", "pll5", "pll1_416"};
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| /kernel/linux/linux-6.6/drivers/clk/mmp/ |
| D | clk-of-pxa1928.c | 41 {0, "pll5", NULL, 0, 1248000000},
146 static const char *sdh_parent_names[] = {"pll1_624", "pll5p", "pll5", "pll1_416"};
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| /kernel/linux/linux-6.6/drivers/clk/sunxi/ |
| D | clk-sunxi.c | 195 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
196 * PLL5 rate is calculated as follows
1017 clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT; in sunxi_divs_clk_setup()
1114 CLK_OF_DECLARE(sun4i_pll5, "allwinner,sun4i-a10-pll5-clk",
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| /kernel/linux/linux-5.10/drivers/clk/sunxi/ |
| D | clk-sunxi.c | 195 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
196 * PLL5 rate is calculated as follows
1017 clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT; in sunxi_divs_clk_setup()
1114 CLK_OF_DECLARE(sun4i_pll5, "allwinner,sun4i-a10-pll5-clk",
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| /kernel/linux/linux-5.10/include/dt-bindings/clock/ |
| D | qcom,gcc-msm8660.h | 258 #define PLL5 249 macro
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| D | qcom,gcc-mdm9615.h | 291 #define PLL5 281 macro
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| /kernel/linux/linux-6.6/include/dt-bindings/clock/ |
| D | qcom,gcc-msm8660.h | 258 #define PLL5 249 macro
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| D | qcom,gcc-mdm9615.h | 291 #define PLL5 281 macro
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