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/kernel/linux/linux-5.10/arch/alpha/kernel/
Dsmc37c669.c58 * er 28-Jan-1997 Initial Entry
67 ** The mask acts as a flag used in mapping actual ISA IRQs (0 - 15)
68 ** to device IRQs (A - H).
81 ** The mask acts as a flag used in mapping actual ISA DMA
82 ** channels to device DMA channels (A - C).
216 ** CR00 - default value 0x28
219 ** 0x - 30ua pull-ups on nIDEEN, nHDCS0, NHDCS1
220 ** 11 - IRQ_H available as IRQ output,
222 ** 10 - nIDEEN, nHDCS0, nHDCS1 used to control IDE
245 ** CR01 - default value 0x9C
[all …]
/kernel/linux/linux-6.6/arch/alpha/kernel/
Dsmc37c669.c58 * er 28-Jan-1997 Initial Entry
67 ** The mask acts as a flag used in mapping actual ISA IRQs (0 - 15)
68 ** to device IRQs (A - H).
81 ** The mask acts as a flag used in mapping actual ISA DMA
82 ** channels to device DMA channels (A - C).
216 ** CR00 - default value 0x28
219 ** 0x - 30ua pull-ups on nIDEEN, nHDCS0, NHDCS1
220 ** 11 - IRQ_H available as IRQ output,
222 ** 10 - nIDEEN, nHDCS0, nHDCS1 used to control IDE
245 ** CR01 - default value 0x9C
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/dsa/
Dqca8k.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Crispin <john@phrozen.org>
13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
14 describing a port needs to have a valid phandle referencing the internal PHY
15 it is connected to. This is because there is no N:N mapping of port and PHY
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
17 the switch node and declare the phandle for the port, referencing the internal
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
[all …]
/kernel/linux/linux-6.6/drivers/net/dsa/mv88e6xxx/
Dport.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Marvell 88E6xxx Switch Port Registers support
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
18 #include "port.h"
21 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, in mv88e6xxx_port_read() argument
24 int addr = chip->info->port_base_addr + port; in mv88e6xxx_port_read()
29 int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg, in mv88e6xxx_port_wait_bit() argument
32 int addr = chip->info->port_base_addr + port; in mv88e6xxx_port_wait_bit()
37 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, in mv88e6xxx_port_write() argument
40 int addr = chip->info->port_base_addr + port; in mv88e6xxx_port_write()
[all …]
Dport.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Marvell 88E6xxx Switch Port Registers support
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
16 /* Offset 0x00: Port Status Register */
28 /* - Modes with PHY suffix use output instead of input clock
29 * - Modes without RMII or RGMII use MII
30 * - Modes without speed do not have a fixed speed specified in the manual
31 * ("DC to x MHz" - variable clock support?)
165 /* Offset 0x04: Port Control Register */
200 /* Offset 0x05: Port Control 1 */
[all …]
Dchip.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Marvell 88E6xxx Ethernet switch single-chip definition
28 /* PVT limits for 4-bit port and 5-bit switch */
110 * enum mv88e6xxx_edsa_support - Ethertype DSA tag support level
115 * empirical data shows that this mode
149 * ports 2-4 are not routet to pins.
152 /* Multi-chip Addressing Mode.
154 * when it is non-zero, and use indirect access to internal registers.
157 /* Dual-chip Addressing Mode
175 * port 0, 1 means internal PHYs range starts at port 1, etc
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/
Dusb251xb.txt1 Microchip USB 2.0 Hi-Speed Hub Controller
4 Hi-Speed Controller.
7 - compatible : Should be "microchip,usb251xb" or one of the specific types:
11 - reg : I2C address on the selected bus (default is <0x2C>)
14 - reset-gpios : Should specify the gpio for hub reset
15 - vdd-supply : Should specify the phandle to the regulator supplying vdd
16 - skip-config : Skip Hub configuration, but only send the USB-Attach command
17 - vendor-id : Set USB Vendor ID of the hub (16 bit, default is 0x0424)
18 - product-id : Set USB Product ID of the hub (16 bit, default depends on type)
19 - device-id : Set USB Device ID of the hub (16 bit, default is 0x0bb3)
[all …]
/kernel/linux/linux-6.6/sound/drivers/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
50 tristate "PC-Speaker support (READ HELP!)"
60 You can compile this as a module which will be called snd-pcsp.
65 pc-speaker a default sound device. Which is likely not
69 options snd-pcsp index=2
71 You don't need this driver if you only want your pc-speaker to beep.
90 will be called snd-dummy.
99 the standard ALSA PCM device. The devices are routed 0->1 and
100 1->0, where first number is the playback PCM device and second
106 timing source using the time shift universal control (+-20%
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/microchip/vcap/
Dvcap_ag_api.h1 /* SPDX-License-Identifier: BSD-3-Clause */
6 /* This file is autogenerated by cml-utils 2023-03-13 10:16:42 +0100.
63 * Used by 802.1BR Bridge Port Extension in an E-Tag
65 * Used by 802.1BR Bridge Port Extension in an E-Tag
67 * Set for frames containing an E-TAG (802.1BR Ethertype 893f)
69 * E-Tag group bits in 802.1BR Bridge Port Extension
71 * Used by 802.1BR Bridge Port Extension in an E-Tag
73 * Used by 802.1BR Bridge Port Extension in an E-Tag
78 * First DEI in multiple vlan tags (outer tag or default port tag)
86 * First PCP in multiple vlan tags (outer tag or default port tag)
[all …]
/kernel/linux/linux-6.6/Documentation/driver-api/
Ddevice-io.rst10 Bus-Independent Device Accesses
27 ----------------------------
49 --------------------
52 memory-mapped registers on the device. Linux provides interfaces to read
53 and write 8-bit, 16-bit, 32-bit and 64-bit quantities. Due to a
82 from config space, which is guaranteed to soft-fail if the card doesn't
94 reg = ha->iobase;
96 WRT_REG_WORD(&reg->ictrl, 0);
102 RD_REG_WORD(&reg->ictrl);
103 ha->flags.ints_enabled = 0;
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/usb/
Dusb251xb.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip USB 2.0 Hi-Speed Hub Controller
10 - Richard Leitner <richard.leitner@skidata.com>
15 - microchip,usb2422
16 - microchip,usb2512b
17 - microchip,usb2512bi
18 - microchip,usb2513b
19 - microchip,usb2513bi
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/bridge/
Dthine,thc63lvd1024.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacopo Mondi <jacopo+renesas@jmondi.org>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
19 Single or dual operation mode, output data mapping and DDR output modes are
32 When operating in single input mode, all pixels are received on port@0,
33 and port@1 shall not contain any endpoint. In dual input mode,
34 even-numbered pixels are received on port@0 and odd-numbered pixels on
35 port@1, and both port@0 and port@1 shall contain endpoints.
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/imx/
Dldb.txt1 Device-Tree bindings for LVDS Display Bridge (ldb)
6 The LVDS Display Bridge device tree node contains up to two lvds-channel
10 - #address-cells : should be <1>
11 - #size-cells : should be <0>
12 - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb".
16 - gpr : should be <&gpr> on i.MX53 and i.MX6q.
17 The phandle points to the iomuxc-gpr region containing the LVDS
19 - clocks, clock-names : phandles to the LDB divider and selector clocks and to
21 Documentation/devicetree/bindings/clock/clock-bindings.txt
23 "di0_pll" - LDB LVDS channel 0 mux
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/imx/
Dldb.txt1 Device-Tree bindings for LVDS Display Bridge (ldb)
6 The LVDS Display Bridge device tree node contains up to two lvds-channel
10 - #address-cells : should be <1>
11 - #size-cells : should be <0>
12 - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb".
16 - gpr : should be <&gpr> on i.MX53 and i.MX6q.
17 The phandle points to the iomuxc-gpr region containing the LVDS
19 - clocks, clock-names : phandles to the LDB divider and selector clocks and to
21 Documentation/devicetree/bindings/clock/clock-bindings.txt
23 "di0_pll" - LDB LVDS channel 0 mux
[all …]
/kernel/linux/linux-5.10/drivers/net/dsa/mv88e6xxx/
Dport.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Marvell 88E6xxx Switch Port Registers support
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
16 /* Offset 0x00: Port Status Register */
134 /* Offset 0x04: Port Control Register */
168 /* Offset 0x05: Port Control 1 */
173 /* Offset 0x06: Port Based VLAN Map */
177 /* Offset 0x07: Default Port VLAN ID & Priority */
181 /* Offset 0x08: Port Control 2 Register */
210 /* Offset 0x0B: Port Association Vector */
[all …]
Dchip.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Marvell 88E6xxx Ethernet switch single-chip definition
24 /* PVT limits for 4-bit port and 5-bit switch */
119 * ports 2-4 are not routet to pins.
122 /* Multi-chip Addressing Mode.
124 * when it is non-zero, and use indirect access to internal registers.
127 /* Dual-chip Addressing Mode
181 /* Port index */
219 enum mv88e6xxx_policy_mapping mapping; member
223 int port; member
[all …]
Dport.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Marvell 88E6xxx Switch Port Registers support
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
17 #include "port.h"
20 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, in mv88e6xxx_port_read() argument
23 int addr = chip->info->port_base_addr + port; in mv88e6xxx_port_read()
28 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, in mv88e6xxx_port_write() argument
31 int addr = chip->info->port_base_addr + port; in mv88e6xxx_port_write()
41 int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port, in mv88e6185_port_set_pause() argument
47 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg); in mv88e6185_port_set_pause()
[all …]
Dglobal1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
18 int addr = chip->info->global1_addr; in mv88e6xxx_g1_read()
25 int addr = chip->info->global1_addr; in mv88e6xxx_g1_write()
33 return mv88e6xxx_wait_bit(chip, chip->info->global1_addr, reg, in mv88e6xxx_g1_wait_bit()
40 return mv88e6xxx_wait_mask(chip, chip->info->global1_addr, reg, in mv88e6xxx_g1_wait_mask()
113 * the PPU, including re-doing PHY detection and initialization in mv88e6185_g1_reset()
218 /* Offset 0x10: IP-PRI Mapping Register 0
219 * Offset 0x11: IP-PRI Mapping Register 1
220 * Offset 0x12: IP-PRI Mapping Register 2
[all …]
/kernel/linux/linux-6.6/include/linux/
Dif_team.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/linux/if_team.h - Network team device driver header
33 int index; /* index of enabled port. If disabled, it's set to -1 */
55 * become a port.
68 struct list_head qom_list; /* node in queue override mapping list */
75 return rcu_dereference(dev->rx_handler_data); in team_port_get_rcu()
78 static inline bool team_port_enabled(struct team_port *port) in team_port_enabled() argument
80 return port->index != -1; in team_port_enabled()
83 static inline bool team_port_txable(struct team_port *port) in team_port_txable() argument
85 return port->linkup && team_port_enabled(port); in team_port_txable()
[all …]
/kernel/linux/linux-5.10/include/linux/
Dif_team.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/linux/if_team.h - Network team device driver header
33 int index; /* index of enabled port. If disabled, it's set to -1 */
55 * become a port.
68 struct list_head qom_list; /* node in queue override mapping list */
75 return rcu_dereference(dev->rx_handler_data); in team_port_get_rcu()
78 static inline bool team_port_enabled(struct team_port *port) in team_port_enabled() argument
80 return port->index != -1; in team_port_enabled()
83 static inline bool team_port_txable(struct team_port *port) in team_port_txable() argument
85 return port->linkup && team_port_enabled(port); in team_port_txable()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/bridge/
Dthine,thc63lvd1024.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacopo Mondi <jacopo+renesas@jmondi.org>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
19 Single or dual operation mode, output data mapping and DDR output modes are
33 The device can operate in single-link mode or dual-link mode. In
34 single-link mode, all pixels are received on port@0, and port@1 shall not
35 contain any endpoint. In dual-link mode, even-numbered pixels are
36 received on port@0 and odd-numbered pixels on port@1, and both port@0 and
[all …]
/kernel/linux/linux-5.10/include/uapi/linux/
Dkd.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
16 unsigned short charheight; /* scan lines per character (1-32) */
39 #define KDADDIO 0x4B34 /* add i/o port as valid */
40 #define KDDELIO 0x4B35 /* del i/o port as valid */
44 #define KDSETMODE 0x4B3A /* set text/graphics mode */
49 #define KDGETMODE 0x4B3B /* get current mode */
56 #define GIO_SCRNMAP 0x4B40 /* get screen mapping from kernel */
57 #define PIO_SCRNMAP 0x4B41 /* put screen mapping table in kernel */
58 #define GIO_UNISCRNMAP 0x4B69 /* get full Unicode screen mapping */
59 #define PIO_UNISCRNMAP 0x4B6A /* set full Unicode screen mapping */
[all …]
/kernel/linux/linux-6.6/include/uapi/linux/
Dkd.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
16 unsigned short charheight; /* scan lines per character (1-32) */
39 #define KDADDIO 0x4B34 /* add i/o port as valid */
40 #define KDDELIO 0x4B35 /* del i/o port as valid */
44 #define KDSETMODE 0x4B3A /* set text/graphics mode */
49 #define KDGETMODE 0x4B3B /* get current mode */
56 #define GIO_SCRNMAP 0x4B40 /* get screen mapping from kernel */
57 #define PIO_SCRNMAP 0x4B41 /* put screen mapping table in kernel */
58 #define GIO_UNISCRNMAP 0x4B69 /* get full Unicode screen mapping */
59 #define PIO_UNISCRNMAP 0x4B6A /* set full Unicode screen mapping */
[all …]
/kernel/linux/linux-5.10/drivers/net/dsa/
Dlantiq_gswip.c1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de>
16 * The hardware does not support VLAN filter on the port, but on the
20 * rule and the CPU port is also added to all bridges. This makes it possible
23 * each switch port which is used when the port is used without an
46 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
64 #define GSWIP_MDIO_PHYp(p) (0x15 - (p))
134 #define GSWIP_BM_RAM_VAL(x) (0x043 - (x))
142 /* buffer management Port Configuration Register */
146 /* buffer management Port Control Register */
[all …]
/kernel/linux/linux-6.6/drivers/ntb/hw/idt/
Dntb_hw_idt.h7 * Copyright (C) 2016-2018 T-Platforms JSC All Rights Reserved.
36 * IDT PCIe-switch NTB Linux driver
39 * Serge Semin <fancer.lancer@gmail.com>, <Sergey.Semin@t-platforms.ru>
55 * the supported IDT PCIe-switches
66 * IDT PCIe-switches device IDs
78 * NT-function Configuration Space registers
79 * NOTE 1) The IDT PCIe-switch internal data is little-endian
83 * with byte-enables corresponding to their native size or
86 * So to simplify the driver code, there is only DWORD-sized read/write
107 /* IDT Proprietary NT-port-specific registers */
[all …]

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