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/kernel/linux/linux-5.10/drivers/staging/sm750fb/
Dddk750_power.c1 // SPDX-License-Identifier: GPL-2.0
30 * On hardware reset, power mode 0 is default.
58 /* Set up other fields in Power Control Register */ in sm750_set_power_mode()
71 /* Program new power mode. */ in sm750_set_power_mode()
75 void sm750_set_current_gate(unsigned int gate) in sm750_set_current_gate() argument
78 poke32(MODE1_GATE, gate); in sm750_set_current_gate()
80 poke32(MODE0_GATE, gate); in sm750_set_current_gate()
88 u32 gate; in sm750_enable_2d_engine() local
90 gate = peek32(CURRENT_GATE); in sm750_enable_2d_engine()
92 gate |= (CURRENT_GATE_DE | CURRENT_GATE_CSC); in sm750_enable_2d_engine()
[all …]
/kernel/linux/linux-6.6/drivers/staging/sm750fb/
Dddk750_power.c1 // SPDX-License-Identifier: GPL-2.0
30 * On hardware reset, power mode 0 is default.
58 /* Set up other fields in Power Control Register */ in sm750_set_power_mode()
71 /* Program new power mode. */ in sm750_set_power_mode()
75 void sm750_set_current_gate(unsigned int gate) in sm750_set_current_gate() argument
78 poke32(MODE1_GATE, gate); in sm750_set_current_gate()
80 poke32(MODE0_GATE, gate); in sm750_set_current_gate()
88 u32 gate; in sm750_enable_2d_engine() local
90 gate = peek32(CURRENT_GATE); in sm750_enable_2d_engine()
92 gate |= (CURRENT_GATE_DE | CURRENT_GATE_CSC); in sm750_enable_2d_engine()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/
Drockchip,rk3399-dmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
15 - rockchip,rk3399-dmc
17 devfreq-events:
21 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt.
26 clock-names:
28 - const: dmc_clk
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/samsung/
Dsamsung,exynos-hdmi.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - samsung,exynos4210-hdmi
19 - samsung,exynos4212-hdmi
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ti/
Ddpll.txt3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped DPLL with usually two selectable input clocks
10 modes (locked, low power stop etc.) This binding has several
11 sub-types, which effectively result in slightly different setup
14 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
17 - compatible : shall be one of:
18 "ti,omap3-dpll-clock",
19 "ti,omap3-dpll-core-clock",
20 "ti,omap3-dpll-per-clock",
21 "ti,omap3-dpll-per-j-type-clock",
[all …]
/kernel/linux/linux-6.6/drivers/clk/mxs/
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
14 * struct clk_pll - mxs pll clock
17 * @power: the shift of power bit
20 * The mxs pll is a fixed rate clock with power and gate control,
21 * and the shift of gate bit is always 31.
26 u8 power; member
36 writel_relaxed(1 << pll->power, pll->base + SET); in clk_pll_prepare()
47 writel_relaxed(1 << pll->power, pll->base + CLR); in clk_pll_unprepare()
54 writel_relaxed(1 << 31, pll->base + CLR); in clk_pll_enable()
[all …]
/kernel/linux/linux-5.10/drivers/clk/mxs/
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
14 * struct clk_pll - mxs pll clock
17 * @power: the shift of power bit
20 * The mxs pll is a fixed rate clock with power and gate control,
21 * and the shift of gate bit is always 31.
26 u8 power; member
36 writel_relaxed(1 << pll->power, pll->base + SET); in clk_pll_prepare()
47 writel_relaxed(1 << pll->power, pll->base + CLR); in clk_pll_unprepare()
54 writel_relaxed(1 << 31, pll->base + CLR); in clk_pll_enable()
[all …]
/kernel/linux/linux-5.10/drivers/clk/samsung/
Dclk-exynos4412-isp.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/clock/exynos4.h>
12 #include <linux/clk-provider.h>
19 /* Exynos4x12 specific registers, which belong to ISP power domain */
48 GATE(CLK_ISP_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0, 0, 0),
49 GATE(CLK_ISP_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1, 0, 0),
50 GATE(CLK_ISP_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2, 0, 0),
51 GATE(CLK_ISP_FIMC_LITE0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, 0, 0),
52 GATE(CLK_ISP_FIMC_LITE1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, 0, 0),
53 GATE(CLK_ISP_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, 0, 0),
[all …]
/kernel/linux/linux-6.6/drivers/clk/samsung/
Dclk-exynos4412-isp.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/clock/exynos4.h>
12 #include <linux/clk-provider.h>
19 /* Exynos4x12 specific registers, which belong to ISP power domain */
51 GATE(CLK_ISP_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0, 0, 0),
52 GATE(CLK_ISP_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1, 0, 0),
53 GATE(CLK_ISP_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2, 0, 0),
54 GATE(CLK_ISP_FIMC_LITE0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, 0, 0),
55 GATE(CLK_ISP_FIMC_LITE1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, 0, 0),
56 GATE(CLK_ISP_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, 0, 0),
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-mmp/
Dpm-mmp2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * MMP2 Power Management Routines
18 #include <asm/mach-types.h>
21 #include "addr-map.h"
22 #include "pm-mmp2.h"
23 #include "regs-icu.h"
29 int irq = d->irq; in mmp2_set_wake()
63 /* close AXI fabric clock gate */ in pm_scu_clk_disable()
67 /* close MCB master clock gate */ in pm_scu_clk_disable()
79 /* open AXI fabric clock gate */ in pm_scu_clk_enable()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dimx8qxp-lpcg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings
10 - Aisheng Dong <aisheng.dong@nxp.com>
13 The Low-Power Clock Gate (LPCG) modules contain a local programming
15 is used to locally gate the clocks for the associated peripheral.
24 include/dt-bindings/clock/imx8-clock.h
29 - fsl,imx8qxp-lpcg-adma
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/iio/gyroscope/
Dinvensense,mpu3050.txt1 Invensense MPU-3050 Gyroscope device tree bindings
4 - compatible : should be "invensense,mpu3050"
5 - reg : the I2C address of the sensor
8 - interrupts : interrupt mapping for the trigger interrupt from the
13 - vdd-supply : supply regulator for the main power voltage.
14 - vlogic-supply : supply regulator for the signal voltage.
15 - mount-matrix : see iio/mount-matrix.txt
18 - The MPU-3050 will pass through and forward the I2C signals from the
21 i2c gate node. For details see: i2c/i2c-gate.txt
28 interrupt-parent = <&foo>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ti/
Ddpll.txt3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped DPLL with usually two selectable input clocks
10 modes (locked, low power stop etc.) This binding has several
11 sub-types, which effectively result in slightly different setup
14 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
17 - compatible : shall be one of:
18 "ti,omap3-dpll-clock",
19 "ti,omap3-dpll-core-clock",
20 "ti,omap3-dpll-per-clock",
21 "ti,omap3-dpll-per-j-type-clock",
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dimx8qxp-lpcg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock
10 - Aisheng Dong <aisheng.dong@nxp.com>
13 The Low-Power Clock Gate (LPCG) modules contain a local programming
15 is used to locally gate the clocks for the associated peripheral.
24 include/dt-bindings/clock/imx8-lpcg.h
29 - const: fsl,imx8qxp-lpcg
[all …]
/kernel/linux/linux-6.6/drivers/media/tuners/
Dfc0013.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net>
11 #include "fc0013-priv.h"
17 .addr = priv->addr, .flags = 0, .buf = buf, .len = 2 in fc0013_writereg()
20 if (i2c_transfer(priv->i2c, &msg, 1) != 1) { in fc0013_writereg()
22 return -EREMOTEIO; in fc0013_writereg()
30 { .addr = priv->addr, .flags = 0, .buf = &reg, .len = 1 }, in fc0013_readreg()
31 { .addr = priv->addr, .flags = I2C_M_RD, .buf = val, .len = 1 }, in fc0013_readreg()
34 if (i2c_transfer(priv->i2c, msg, 2) != 2) { in fc0013_readreg()
36 return -EREMOTEIO; in fc0013_readreg()
[all …]
/kernel/linux/linux-5.10/drivers/media/tuners/
Dfc0013.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net>
11 #include "fc0013-priv.h"
17 .addr = priv->addr, .flags = 0, .buf = buf, .len = 2 in fc0013_writereg()
20 if (i2c_transfer(priv->i2c, &msg, 1) != 1) { in fc0013_writereg()
22 return -EREMOTEIO; in fc0013_writereg()
30 { .addr = priv->addr, .flags = 0, .buf = &reg, .len = 1 }, in fc0013_readreg()
31 { .addr = priv->addr, .flags = I2C_M_RD, .buf = val, .len = 1 }, in fc0013_readreg()
34 if (i2c_transfer(priv->i2c, msg, 2) != 2) { in fc0013_readreg()
36 return -EREMOTEIO; in fc0013_readreg()
[all …]
/kernel/linux/linux-6.6/drivers/clk/x86/
Dclk-cgu.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020-2022 MaxLinear, Inc.
8 #include <linux/clk-provider.h>
12 #include "clk-cgu.h"
29 if (list->div_flags & CLOCK_FLAG_VAL_INIT) in lgm_clk_register_fixed()
30 lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift, in lgm_clk_register_fixed()
31 list->div_width, list->div_val); in lgm_clk_register_fixed()
33 return clk_hw_register_fixed_rate(NULL, list->name, in lgm_clk_register_fixed()
34 list->parent_data[0].name, in lgm_clk_register_fixed()
35 list->flags, list->mux_flags); in lgm_clk_register_fixed()
[all …]
/kernel/linux/linux-5.10/drivers/clk/x86/
Dclk-cgu.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020-2022 MaxLinear, Inc.
8 #include <linux/clk-provider.h>
12 #include "clk-cgu.h"
29 if (list->div_flags & CLOCK_FLAG_VAL_INIT) in lgm_clk_register_fixed()
30 lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift, in lgm_clk_register_fixed()
31 list->div_width, list->div_val); in lgm_clk_register_fixed()
33 return clk_hw_register_fixed_rate(NULL, list->name, in lgm_clk_register_fixed()
34 list->parent_data[0].name, in lgm_clk_register_fixed()
35 list->flags, list->mux_flags); in lgm_clk_register_fixed()
[all …]
/kernel/linux/linux-6.6/include/dt-bindings/clock/
Dtegra234-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
14 /** @brief output of gate CLK_ENB_ADSP */
16 /** @brief output of gate CLK_ENB_ADSPNEON */
20 /** @brief output of gate CLK_ENB_APB2APE */
30 /** @brief output of gate CLK_ENB_CAN1_HOST */
34 /** @brief output of gate CLK_ENB_CAN2_HOST */
46 /** @brief output of gate CLK_ENB_DPAUX */
78 * throughput and memory controller power.
85 /** @brief output of gate CLK_ENB_EQOS_RX */
[all …]
Dhi6220-clock.h1 /* SPDX-License-Identifier: GPL-2.0-only */
41 /* gate clocks */
60 /* gate clock */
124 /* gate clock */
130 /* gate clocks */
161 /* clk in Hi6220 power controller */
162 /* gate clocks */
/kernel/linux/linux-5.10/include/dt-bindings/clock/
Dhi6220-clock.h1 /* SPDX-License-Identifier: GPL-2.0-only */
41 /* gate clocks */
60 /* gate clock */
124 /* gate clock */
130 /* gate clocks */
161 /* clk in Hi6220 power controller */
162 /* gate clocks */
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Dhisilicon-histb-pcie.txt6 Documentation/devicetree/bindings/pci/designware-pcie.txt.
11 - compatible: Should be one of the following strings:
12 "hisilicon,hi3798cv200-pcie"
13 - reg: Should contain sysctl, rc_dbi, config registers location and length.
14 - reg-names: Must include the following entries:
16 "rc-dbi": configuration space of PCIe controller;
18 - bus-range: PCI bus numbers covered.
19 - interrupts: MSI interrupt.
20 - interrupt-names: Must include "msi" entries.
21 - clocks: List of phandle and clock specifier pairs as listed in clock-names
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/
Dhisilicon-histb-pcie.txt6 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
11 - compatible: Should be one of the following strings:
12 "hisilicon,hi3798cv200-pcie"
13 - reg: Should contain sysctl, rc_dbi, config registers location and length.
14 - reg-names: Must include the following entries:
16 "rc-dbi": configuration space of PCIe controller;
18 - bus-range: PCI bus numbers covered.
19 - interrupts: MSI interrupt.
20 - interrupt-names: Must include "msi" entries.
21 - clocks: List of phandle and clock specifier pairs as listed in clock-names
[all …]
/kernel/linux/linux-6.6/drivers/clk/pxa/
Dclk-pxa.h1 /* SPDX-License-Identifier: GPL-2.0-only */
92 * - a low power parent
93 * - a normal parent
95 * +------------+ +-----------+
96 * | Low Power | --- | x mult_lp |
98 * +------------+ +-----------+ \+-----+ +-----------+
99 * | Mux |---| CKEN gate |
100 * +------------+ +-----------+ /+-----+ +-----------+
101 * | High Power | | x mult_hp |/
102 * | Clock | --- | / div_hp |
[all …]
/kernel/linux/linux-5.10/drivers/clk/pxa/
Dclk-pxa.h1 /* SPDX-License-Identifier: GPL-2.0-only */
92 * - a low power parent
93 * - a normal parent
95 * +------------+ +-----------+
96 * | Low Power | --- | x mult_lp |
98 * +------------+ +-----------+ \+-----+ +-----------+
99 * | Mux |---| CKEN gate |
100 * +------------+ +-----------+ /+-----+ +-----------+
101 * | High Power | | x mult_hp |/
102 * | Clock | --- | / div_hp |
[all …]

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