| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_atombios.c | 569 struct amdgpu_pll *ppll = &adev->clock.ppll[0]; in amdgpu_atombios_get_clock_info() local
576 ppll->reference_freq = in amdgpu_atombios_get_clock_info()
578 ppll->reference_div = 0; in amdgpu_atombios_get_clock_info()
580 ppll->pll_out_min = in amdgpu_atombios_get_clock_info()
582 ppll->pll_out_max = in amdgpu_atombios_get_clock_info()
585 ppll->lcd_pll_out_min = in amdgpu_atombios_get_clock_info()
587 if (ppll->lcd_pll_out_min == 0) in amdgpu_atombios_get_clock_info()
588 ppll->lcd_pll_out_min = ppll->pll_out_min; in amdgpu_atombios_get_clock_info()
589 ppll->lcd_pll_out_max = in amdgpu_atombios_get_clock_info()
591 if (ppll->lcd_pll_out_max == 0) in amdgpu_atombios_get_clock_info()
[all …]
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| D | amdgpu_pll.c | 288 * amdgpu_pll_get_shared_dp_ppll - return the PPLL used by another crtc for DP
292 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
293 * also in DP mode. For DP, a single PPLL can be used for all DP
317 * amdgpu_pll_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
321 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
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| D | dce_v8_0.c | 2112 * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
2116 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2117 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2118 * monitors a dedicated PPLL must be used. If a particular board has
2143 /* skip PPLL programming if using ext clock */ in dce_v8_0_pick_pll()
2146 /* use the same PPLL for all DP monitors */ in dce_v8_0_pick_pll()
2152 /* use the same PPLL for all monitors with the same clock */ in dce_v8_0_pick_pll()
2166 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v8_0_pick_pll()
2177 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v8_0_pick_pll()
2493 /* disable the ppll */ in dce_v8_0_crtc_disable()
[all …]
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| D | dce_v11_0.c | 2259 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2263 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2264 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2265 * monitors a dedicated PPLL must be used. If a particular board has
2323 /* skip PPLL programming if using ext clock */ in dce_v11_0_pick_pll()
2326 /* use the same PPLL for all DP monitors */ in dce_v11_0_pick_pll()
2332 /* use the same PPLL for all monitors with the same clock */ in dce_v11_0_pick_pll()
2345 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v11_0_pick_pll()
2354 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v11_0_pick_pll()
2673 /* disable the ppll */ in dce_v11_0_crtc_disable()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_atombios.c | 569 struct amdgpu_pll *ppll = &adev->clock.ppll[0]; in amdgpu_atombios_get_clock_info() local
576 ppll->reference_freq = in amdgpu_atombios_get_clock_info()
578 ppll->reference_div = 0; in amdgpu_atombios_get_clock_info()
580 ppll->pll_out_min = in amdgpu_atombios_get_clock_info()
582 ppll->pll_out_max = in amdgpu_atombios_get_clock_info()
585 ppll->lcd_pll_out_min = in amdgpu_atombios_get_clock_info()
587 if (ppll->lcd_pll_out_min == 0) in amdgpu_atombios_get_clock_info()
588 ppll->lcd_pll_out_min = ppll->pll_out_min; in amdgpu_atombios_get_clock_info()
589 ppll->lcd_pll_out_max = in amdgpu_atombios_get_clock_info()
591 if (ppll->lcd_pll_out_max == 0) in amdgpu_atombios_get_clock_info()
[all …]
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| D | amdgpu_pll.c | 279 * amdgpu_pll_get_shared_dp_ppll - return the PPLL used by another crtc for DP
283 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
284 * also in DP mode. For DP, a single PPLL can be used for all DP
308 * amdgpu_pll_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
313 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
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| D | dce_v8_0.c | 2118 * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
2122 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2123 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2124 * monitors a dedicated PPLL must be used. If a particular board has
2149 /* skip PPLL programming if using ext clock */ in dce_v8_0_pick_pll()
2152 /* use the same PPLL for all DP monitors */ in dce_v8_0_pick_pll()
2158 /* use the same PPLL for all monitors with the same clock */ in dce_v8_0_pick_pll()
2172 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v8_0_pick_pll()
2183 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v8_0_pick_pll()
2499 /* disable the ppll */ in dce_v8_0_crtc_disable()
[all …]
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| D | dce_v11_0.c | 2261 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2265 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2266 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2267 * monitors a dedicated PPLL must be used. If a particular board has
2328 /* skip PPLL programming if using ext clock */ in dce_v11_0_pick_pll()
2331 /* use the same PPLL for all DP monitors */ in dce_v11_0_pick_pll()
2337 /* use the same PPLL for all monitors with the same clock */ in dce_v11_0_pick_pll()
2350 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v11_0_pick_pll()
2359 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v11_0_pick_pll()
2678 /* disable the ppll */ in dce_v11_0_crtc_disable()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
| D | atombios_crtc.c | 1753 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1757 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1758 * also in DP mode. For DP, a single PPLL can be used for all DP
1787 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1792 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1838 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1842 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
1843 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
1844 * monitors a dedicated PPLL must be used. If a particular board has
1887 /* skip PPLL programming if using ext clock */ in radeon_atom_pick_pll()
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/radeon/ |
| D | atombios_crtc.c | 1742 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1746 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1747 * also in DP mode. For DP, a single PPLL can be used for all DP
1776 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1780 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1826 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1830 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
1831 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
1832 * monitors a dedicated PPLL must be used. If a particular board has
1875 /* skip PPLL programming if using ext clock */ in radeon_atom_pick_pll()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/imx/ |
| D | clk-imx35.c | 61 static const char *std_sel[] = {"ppll", "arm"};
65 /* 0 */ ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, enumerator
110 clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL); in _mx35_clocks_init()
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| /kernel/linux/linux-6.6/drivers/clk/imx/ |
| D | clk-imx35.c | 60 static const char *std_sel[] = {"ppll", "arm"};
64 /* 0 */ ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, enumerator
109 clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL); in _mx35_clocks_init()
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| /kernel/linux/linux-6.6/drivers/clk/rockchip/ |
| D | clk-rk3399.c | 23 ppll, enumerator
136 PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll", "gpll", "ppll" };
140 "ppll" };
145 PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll",
150 "ppll", "upll", "xin24m" };
210 PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" };
211 PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" };
236 [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, 0, RK3399_PMU_PLL_CON(0),
1407 GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", 0,
1428 COMPOSITE_NOMUX(SCLK_I2C0_PMU, "clk_i2c0_pmu", "ppll", 0,
[all …]
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| D | clk-rk3588.c | 41 b0pll, b1pll, lpll, v0pll, aupll, cpll, gpll, npll, ppll, enumerator
533 PNAME(mux_24m_ppll_spll_p) = { "xin24m", "ppll", "spll" };
534 PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" };
692 [ppll] = PLL(pll_rk3588_core, PLL_PPLL, "ppll", mux_pll_p,
2163 COMPOSITE_NOMUX(CLK_REF_PIPE_PHY0_PLL_SRC, "clk_ref_pipe_phy0_pll_src", "ppll", 0,
2166 COMPOSITE_NOMUX(CLK_REF_PIPE_PHY1_PLL_SRC, "clk_ref_pipe_phy1_pll_src", "ppll", 0,
2169 COMPOSITE_NOMUX(CLK_REF_PIPE_PHY2_PLL_SRC, "clk_ref_pipe_phy2_pll_src", "ppll", 0,
2310 GATE(CLK_PHY0_REF_ALT_P, "clk_phy0_ref_alt_p", "ppll", 0,
2312 GATE(CLK_PHY0_REF_ALT_M, "clk_phy0_ref_alt_m", "ppll", 0,
2314 GATE(CLK_PHY1_REF_ALT_P, "clk_phy1_ref_alt_p", "ppll", 0,
[all …]
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| D | clk-rk3568.c | 19 ppll, hpll, enumerator
289 PNAME(ppll_usb480m_cpll_gpll_p) = { "ppll", "usb480m", "cpll", "gpll"};
307 PNAME(clk_pdpmu_p) = { "ppll", "gpll" };
308 PNAME(clk_mac_2top_p) = { "cpll_125m", "cpll_50m", "cpll_25m", "ppll" };
314 [ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p,
1462 FACTOR(0, "ppll_ph0", "ppll", 0, 1, 2),
1463 FACTOR(0, "ppll_ph180", "ppll", 0, 1, 2),
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| /kernel/linux/linux-5.10/drivers/clk/rockchip/ |
| D | clk-rk3399.c | 23 ppll, enumerator
136 PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll", "gpll", "ppll" };
140 "ppll" };
145 PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll",
150 "ppll", "upll", "xin24m" };
210 PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" };
211 PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" };
236 [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, 0, RK3399_PMU_PLL_CON(0),
1405 GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", 0,
1426 COMPOSITE_NOMUX(SCLK_I2C0_PMU, "clk_i2c0_pmu", "ppll", 0,
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/include/ |
| D | bios_parser_types.h | 206 * other ppll params */
209 * other ppll params */
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/include/ |
| D | bios_parser_types.h | 208 * other ppll params */
211 * other ppll params */
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | imx35-clock.yaml | 21 ppll 2
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | imx35-clock.yaml | 21 ppll 2
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| /kernel/linux/linux-6.6/include/dt-bindings/clock/ |
| D | xlnx-versal-clk.h | 19 #define PPLL 10 macro
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| /kernel/linux/linux-5.10/include/dt-bindings/clock/ |
| D | xlnx-versal-clk.h | 19 #define PPLL 10 macro
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| /kernel/linux/linux-6.6/Documentation/gpu/amdgpu/display/ |
| D | dc-glossary.rst | 41 * PPLL: Pixel PLL
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| /kernel/linux/linux-5.10/drivers/video/fbdev/aty/ |
| D | radeon_base.c | 1364 /* We still have to force a switch to selected PPLL div thanks to in radeon_write_pll_regs()
1376 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/ in radeon_write_pll_regs()
1379 /* Reset PPLL & enable atomic update */ in radeon_write_pll_regs()
1384 /* Switch to selected PPLL divider */ in radeon_write_pll_regs()
1391 /* Set PPLL ref. div */ in radeon_write_pll_regs()
1410 /* Set PPLL divider 3 & post divider*/ in radeon_write_pll_regs()
1436 /* Switch back VCLK source to PPLL */ in radeon_write_pll_regs()
1825 /* Calculate PPLL value if necessary */ in radeonfb_set_par()
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| /kernel/linux/linux-6.6/drivers/video/fbdev/aty/ |
| D | radeon_base.c | 1365 /* We still have to force a switch to selected PPLL div thanks to in radeon_write_pll_regs()
1377 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/ in radeon_write_pll_regs()
1380 /* Reset PPLL & enable atomic update */ in radeon_write_pll_regs()
1385 /* Switch to selected PPLL divider */ in radeon_write_pll_regs()
1392 /* Set PPLL ref. div */ in radeon_write_pll_regs()
1411 /* Set PPLL divider 3 & post divider*/ in radeon_write_pll_regs()
1437 /* Switch back VCLK source to PPLL */ in radeon_write_pll_regs()
1826 /* Calculate PPLL value if necessary */ in radeonfb_set_par()
|