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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dstericsson,u8500-clks.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DB8500 (U8500) clocks
10 - Ulf Hansson <ulf.hansson@linaro.org>
11 - Linus Walleij <linus.walleij@linaro.org>
14 DB8500 digital baseband system-on-chip and its siblings such as
16 itself, not off-chip clocks. There are four different on-chip
17 clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dux500.txt1 Clock bindings for ST-Ericsson Ux500 clocks
4 - compatible : shall contain only one of the following:
5 "stericsson,u8500-clks"
6 "stericsson,u8540-clks"
7 "stericsson,u9540-clks"
8 - reg : shall contain base register location and length for
13 - prcmu-clock: a subnode with one clock cell for PRCMU (power,
14 reset, control unit) clocks. The cell indicates which PRCMU
15 clock in the prcmu-clock node the consumer wants to use.
16 - prcc-periph-clock: a subnode with two clock cells for
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dste-dbx5x0.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/mfd/dbx500-prcmu.h>
9 #include <dt-bindings/arm/ux500_pm_domains.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/thermal/thermal.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
37 #address-cells = <1>;
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/kernel/linux/linux-5.10/drivers/mfd/
Ddb8500-prcmu.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) ST-Ericsson SA 2010
35 #include <linux/mfd/dbx500-prcmu.h>
37 #include <linux/regulator/db8500-prcmu.h>
40 #include "dbx500-prcmu-regs.h"
228 #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
273 * communication with the PRCMU firmware.
333 #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
348 * mb0_transfer - state needed for mailbox 0 communication.
369 * mb1_transfer - state needed for mailbox 1 communication.
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/kernel/linux/linux-6.6/drivers/mfd/
Ddb8500-prcmu.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) ST-Ericsson SA 2010
35 #include <linux/mfd/dbx500-prcmu.h>
37 #include <linux/regulator/db8500-prcmu.h>
39 #include "db8500-prcmu-regs.h"
227 #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
272 * communication with the PRCMU firmware.
332 #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
347 * mb0_transfer - state needed for mailbox 0 communication.
368 * mb1_transfer - state needed for mailbox 1 communication.
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Ddb8500-prcmu-regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) ST-Ericsson SA 2010
15 #define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end))
114 /* PRCMU clock/PLL/reset registers */
183 /* PRCMU HW semaphore */
/kernel/linux/linux-5.10/drivers/clocksource/
Dclksrc-dbx500-prcmu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson SA 2011
5 * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson
6 * Author: Sundar Iyer for ST-Ericsson
8 * plat-nomadik/timer.c Linus Walleij <linus.walleij@stericsson.com>
10 * DBx500-PRCMU Timer
11 * The PRCMU has 5 timers which are available in a always-on
12 * power domain. We use the Timer 4 for our always-on clock
45 .name = "dbx500-prcmu-timer",
59 * The PRCMU should configure it but if it for some reason in clksrc_dbx500_prcmu_init()
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/kernel/linux/linux-6.6/drivers/clocksource/
Dclksrc-dbx500-prcmu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson SA 2011
5 * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson
6 * Author: Sundar Iyer for ST-Ericsson
8 * plat-nomadik/timer.c Linus Walleij <linus.walleij@stericsson.com>
10 * DBx500-PRCMU Timer
11 * The PRCMU has 5 timers which are available in a always-on
12 * power domain. We use the Timer 4 for our always-on clock
45 .name = "dbx500-prcmu-timer",
59 * The PRCMU should configure it but if it for some reason in clksrc_dbx500_prcmu_init()
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/kernel/linux/linux-6.6/arch/arm/boot/dts/st/
Dste-dbx5x0.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/ste-db8500-clkout.h>
9 #include <dt-bindings/reset/stericsson,db8500-prcc-reset.h>
10 #include <dt-bindings/mfd/dbx500-prcmu.h>
11 #include <dt-bindings/arm/ux500_pm_domains.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/thermal/thermal.h>
16 #address-cells = <1>;
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/kernel/linux/linux-6.6/include/linux/mfd/
Ddbx500-prcmu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * STE Ux500 PRCMU API
14 #include <dt-bindings/mfd/dbx500-prcmu.h> /* For clock identifiers */
20 /* PRCMU Wakeup defines */
40 * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
41 * - EPOD_ID_SVAPIPE: power domain for SVA pipe
42 * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
43 * - EPOD_ID_SIAPIPE: power domain for SIA pipe
44 * - EPOD_ID_SGA: power domain for SGA
45 * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
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Ddb8500-prcmu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) ST-Ericsson SA 2010
8 * PRCMU f/w APIs
27 /* This portion previously known as <mach/prcmu-fw-defs_v1.h> */
30 * enum state - ON/OFF state definition
41 * enum ret_state - general purpose On/Off/Retention states
51 * enum clk_arm - ARM Cortex A9 clock schemes
67 * enum clk_gen - GEN#0/GEN#1 clock schemes
81 * enum romcode_write - Romcode message written by A9 AND read by XP70
84 * romcode. The xp70 will go into self-reset
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/kernel/linux/linux-5.10/include/linux/mfd/
Ddbx500-prcmu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * STE Ux500 PRCMU API
14 #include <dt-bindings/mfd/dbx500-prcmu.h> /* For clock identifiers */
20 /* PRCMU Wakeup defines */
40 * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
41 * - EPOD_ID_SVAPIPE: power domain for SVA pipe
42 * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
43 * - EPOD_ID_SIAPIPE: power domain for SIA pipe
44 * - EPOD_ID_SGA: power domain for SGA
45 * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
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Ddb8500-prcmu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) ST-Ericsson SA 2010
8 * PRCMU f/w APIs
27 /* This portion previously known as <mach/prcmu-fw-defs_v1.h> */
30 * enum state - ON/OFF state definition
41 * enum ret_state - general purpose On/Off/Retention states
51 * enum clk_arm - ARM Cortex A9 clock schemes
67 * enum clk_gen - GEN#0/GEN#1 clock schemes
81 * enum romcode_write - Romcode message written by A9 AND read by XP70
84 * romcode. The xp70 will go into self-reset
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/kernel/linux/linux-5.10/drivers/gpu/drm/mcde/
Dmcde_dsi.c1 // SPDX-License-Identifier: GPL-2.0+
32 /* PRCMU DSI reset registers */
54 struct regmap *prcmu; member
73 d = host_to_mcde_dsi(mdsi->host); in mcde_dsi_irq()
75 dev_dbg(d->dev, "%s called\n", __func__); in mcde_dsi_irq()
77 val = readl(d->regs + DSI_DIRECT_CMD_STS_FLAG); in mcde_dsi_irq()
79 dev_dbg(d->dev, "DSI_DIRECT_CMD_STS_FLAG = %08x\n", val); in mcde_dsi_irq()
81 dev_dbg(d->dev, "direct command write completed\n"); in mcde_dsi_irq()
84 dev_dbg(d->dev, "direct command TE received\n"); in mcde_dsi_irq()
87 dev_err(d->dev, "direct command ACK ERR received\n"); in mcde_dsi_irq()
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/kernel/linux/linux-6.6/drivers/gpu/drm/mcde/
Dmcde_dsi.c1 // SPDX-License-Identifier: GPL-2.0+
32 /* PRCMU DSI reset registers */
54 struct regmap *prcmu; member
73 d = host_to_mcde_dsi(mdsi->host); in mcde_dsi_irq()
75 dev_dbg(d->dev, "%s called\n", __func__); in mcde_dsi_irq()
77 val = readl(d->regs + DSI_DIRECT_CMD_STS_FLAG); in mcde_dsi_irq()
79 dev_dbg(d->dev, "DSI_DIRECT_CMD_STS_FLAG = %08x\n", val); in mcde_dsi_irq()
81 dev_dbg(d->dev, "direct command write completed\n"); in mcde_dsi_irq()
84 dev_dbg(d->dev, "direct command TE received\n"); in mcde_dsi_irq()
87 dev_err(d->dev, "direct command ACK ERR received\n"); in mcde_dsi_irq()
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/kernel/linux/linux-5.10/drivers/clk/ux500/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 # Clock types
7 obj-y += clk-prcc.o
8 obj-y += clk-prcmu.o
9 obj-y += clk-sysctrl.o
11 # Clock definitions
12 obj-y += u8500_of_clk.o
14 # ABX500 clock driver
15 obj-y += abx500-clk.o
Du8500_of_clk.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Clock definitions for u8500 platform.
5 * Copyright (C) 2012 ST-Ericsson SA
11 #include <linux/clk-provider.h>
12 #include <linux/mfd/dbx500-prcmu.h>
35 if (clkspec->args_count != 2) in ux500_twocell_get()
36 return ERR_PTR(-EINVAL); in ux500_twocell_get()
38 base = clkspec->args[0]; in ux500_twocell_get()
39 bit = clkspec->args[1]; in ux500_twocell_get()
43 return ERR_PTR(-EINVAL); in ux500_twocell_get()
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Dclk-prcmu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PRCMU clock implementation for ux500 platform.
5 * Copyright (C) 2012 ST-Ericsson SA
9 #include <linux/clk-provider.h>
10 #include <linux/mfd/dbx500-prcmu.h>
26 /* PRCMU clock operations. */
33 ret = prcmu_request_clock(clk->cg_sel, true); in clk_prcmu_prepare()
35 clk->is_prepared = 1; in clk_prcmu_prepare()
43 if (prcmu_request_clock(clk->cg_sel, false)) in clk_prcmu_unprepare()
47 clk->is_prepared = 0; in clk_prcmu_unprepare()
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/kernel/linux/linux-6.6/drivers/clk/ux500/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 # Clock types
7 obj-y += clk-prcc.o
8 obj-y += clk-prcmu.o
9 obj-y += clk-sysctrl.o
12 obj-y += reset-prcc.o
14 # Clock definitions
15 obj-y += u8500_of_clk.o
17 # ABX500 clock driver
18 obj-y += abx500-clk.o
Dclk-prcmu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PRCMU clock implementation for ux500 platform.
5 * Copyright (C) 2012 ST-Ericsson SA
9 #include <linux/clk-provider.h>
10 #include <linux/mfd/dbx500-prcmu.h>
32 /* PRCMU clock operations. */
38 return prcmu_request_clock(clk->cg_sel, true); in clk_prcmu_prepare()
44 if (prcmu_request_clock(clk->cg_sel, false)) in clk_prcmu_unprepare()
53 return prcmu_clock_rate(clk->cg_sel); in clk_prcmu_recalc_rate()
60 return prcmu_round_clock_rate(clk->cg_sel, rate); in clk_prcmu_round_rate()
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/timer/
Dst,nomadik-mtu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/timer/st,nomadik-mtu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: ST Microelectronics Nomadik Multi-Timer Unit MTU Timer
11 - Linus Walleij <linus.walleij@linaro.org>
14 SoCs STn8800, STn8810 and STn8815 as well as in ST-Ericsson DB8500.
19 - const: st,nomadik-mtu
28 description: The first clock named TIMCLK clocks the actual timers and
29 the second clock clocks the digital interface to the interconnect.
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mfd/
Dstericsson,ab8500.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson Analog Baseband AB8500 and AB8505
10 - Linus Walleij <linus.walleij@linaro.org>
13 the AB8500 "Analog Baseband" is the mixed-signals integrated circuit
14 handling power management (regulators), analog-to-digital conversion
15 (ADC), battery charging, fuel gauging of the battery, battery-backed
16 RTC, PWM, USB PHY and some GPIO lines in the ST-Ericsson U8500 platforms
17 in connection with the DB8500 digital baseband. The DB8500 PRCMU
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/kernel/linux/linux-5.10/include/dt-bindings/mfd/
Ddbx500-prcmu.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * This header provides constants for the PRCMU bindings.
11 * Clock identifiers.
74 /* LCD DSI PLL - Ux540 only */
/kernel/linux/linux-6.6/include/dt-bindings/mfd/
Ddbx500-prcmu.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * This header provides constants for the PRCMU bindings.
11 * Clock identifiers.
74 /* LCD DSI PLL - Ux540 only */
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/
Dste,mcde.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson Multi Channel Display Engine MCDE
10 - Linus Walleij <linus.walleij@linaro.org>
25 - description: MCDECLK (main MCDE clock)
26 - description: LCDCLK (LCD clock)
27 - description: PLLDSI (HDMI clock)
29 clock-names:
31 - const: mcde
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