| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/input/ |
| D | ti,drv260x.txt | 1 * Texas Instruments - drv260x Haptics driver family
4 - compatible - One of:
5 "ti,drv2604" - DRV2604
6 "ti,drv2605" - DRV2605
7 "ti,drv2605l" - DRV2605L
8 - reg - I2C slave address
9 - vbat-supply - Required supply regulator
10 - mode - Power up mode of the chip (defined in include/dt-bindings/input/ti-drv260x.h)
11 DRV260X_LRA_MODE - Linear Resonance Actuator mode (Piezoelectric)
12 DRV260X_LRA_NO_CAL_MODE - This is a LRA Mode but there is no calibration
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/input/ |
| D | ti,drv260x.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments - drv260x Haptics driver family
10 - Andrew Davis <afd@ti.com>
15 - ti,drv2604
16 - ti,drv2605
17 - ti,drv2605l
22 vbat-supply:
30 (defined in include/dt-bindings/input/ti-drv260x.h)
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/power/supply/ |
| D | richtek,rt5033-charger.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/supply/richtek,rt5033-charger.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jakob Hauser <jahau@rocketmail.com>
14 under sub-node named "charger" using the following format.
18 const: richtek,rt5033-charger
20 monitored-battery:
26 precharge-current-microamp:
27 Current of pre-charge mode. The pre-charge current levels are 350 mA
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| /kernel/linux/linux-6.6/Documentation/gpu/amdgpu/display/ |
| D | display-manager.rst | 8 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
17 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
20 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
26 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
29 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
32 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
38 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
41 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
47 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
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| D | dcn-overview.rst | 10 .. kernel-figure:: dc_pipeline_overview.svg
19 * **Display Pipe and Plane (DPP)**: This block provides pre-blend pixel
24 multiple planes, using global or per-pixel alpha.
38 * **Multi-Media HUB (MMHUBBUB)**: Memory controller interface for DMCUB and DWB
43 the Display Micro-Controller Unit - version B (DMCUB), which is handled via
84 ----------------------
100 a one-to-one mapping of the link encoder to PHY, but we can configure the DCN
106 ---------
114 representation and convert them to a DCN specific floating-point format (i.e.,
115 different from the IEEE floating-point format). In the process, CNVC also
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| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/ |
| D | intel_wopcm.c | 1 // SPDX-License-Identifier: MIT
3 * Copyright © 2017-2019 Intel Corporation
26 * | Size +--------------------+
28 * | | +--------------------+
30 * | | +------------------- +
34 * | +------------------- + <== HuC Firmware Top
73 * intel_wopcm_init_early() - Early initialization of the WOPCM.
81 struct drm_i915_private *i915 = gt->i915; in intel_wopcm_init_early()
87 wopcm->size = GEN11_WOPCM_SIZE; in intel_wopcm_init_early()
89 wopcm->size = GEN9_WOPCM_SIZE; in intel_wopcm_init_early()
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mtd/ |
| D | mtd.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
19 User-defined MTD device name. Can be used to assign user friendly
24 '#address-cells':
27 '#size-cells':
34 - compatible
37 "@[0-9a-f]+$":
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| /kernel/linux/linux-6.6/drivers/mtd/chips/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
13 support any device that is CFI-compliant, you need to enable this
18 tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
22 This option enables JEDEC-style probing of flash chips which are not
24 CFI-targeted flash drivers for any chips which are identified which
26 covers most AMD/Fujitsu-compatible chips and also non-CFI
53 are expected to be wired to the CPU in 'host-endian' form.
85 bool "Support 8-bit buswidth" if MTD_CFI_GEOMETRY
92 bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
99 bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
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| /kernel/linux/linux-5.10/drivers/mtd/chips/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
13 support any device that is CFI-compliant, you need to enable this
18 tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
22 This option enables JEDEC-style probing of flash chips which are not
24 CFI-targeted flash drivers for any chips which are identified which
26 covers most AMD/Fujitsu-compatible chips and also non-CFI
53 are expected to be wired to the CPU in 'host-endian' form.
85 bool "Support 8-bit buswidth" if MTD_CFI_GEOMETRY
92 bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
99 bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | silabs,si5341.txt | 6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
28 still be programmed into the chip and the driver will leave them "as is".
33 - compatible: shall be one of the following:
34 "silabs,si5340" - Si5340 A/B/C/D
35 "silabs,si5341" - Si5341 A/B/C/D
36 "silabs,si5342" - Si5342 A/B/C/D
37 "silabs,si5344" - Si5344 A/B/C/D
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | silabs,si5341.txt | 6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
28 fancy input configurations. They can still be programmed into the chip and
34 - compatible: shall be one of the following:
35 "silabs,si5340" - Si5340 A/B/C/D
36 "silabs,si5341" - Si5341 A/B/C/D
37 "silabs,si5342" - Si5342 A/B/C/D
38 "silabs,si5344" - Si5344 A/B/C/D
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| /kernel/linux/linux-6.6/Documentation/trace/coresight/ |
| D | coresight-config.rst | 1 .. SPDX-License-Identifier: GPL-2.0
14 programming of the CoreSight system with pre-defined configurations that
17 Many CoreSight components can be programmed in complex ways - especially ETMs.
30 --------
41 accesses in the driver - the resource usage and parameter descriptions
43 and efficient for the feature to be programmed onto the device when required.
47 will be programmed into the device hardware.
56 feature being enabled that can adjust the behaviour of the operation programmed
59 For example, this could be a count value in a programmed operation that repeats
67 system - which is described below.
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| /kernel/linux/linux-6.6/drivers/clk/samsung/ |
| D | clk-cpu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
22 * registers to acheive a fast co-oridinated rate change for all the CPU domain
36 #include <linux/clk-provider.h>
37 #include "clk-cpu.h"
101 pr_err("%s: re-parenting mux timed-out\n", __func__); in wait_until_mux_stable()
135 * dividers to be programmed.
148 /* handler for pre-rate change notification from parent clock */
152 const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg; in exynos_cpuclk_pre_rate_change()
153 unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent); in exynos_cpuclk_pre_rate_change()
159 while ((cfg_data->prate * 1000) != ndata->new_rate) { in exynos_cpuclk_pre_rate_change()
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| /kernel/linux/linux-5.10/drivers/clk/samsung/ |
| D | clk-cpu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
22 * registers to acheive a fast co-oridinated rate change for all the CPU domain
36 #include <linux/clk-provider.h>
37 #include "clk-cpu.h"
101 pr_err("%s: re-parenting mux timed-out\n", __func__); in wait_until_mux_stable()
135 * dividers to be programmed.
148 /* handler for pre-rate change notification from parent clock */
152 const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg; in exynos_cpuclk_pre_rate_change()
153 unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent); in exynos_cpuclk_pre_rate_change()
159 while ((cfg_data->prate * 1000) != ndata->new_rate) { in exynos_cpuclk_pre_rate_change()
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| /kernel/linux/linux-5.10/drivers/clk/analogbits/ |
| D | wrpll-cln28hpc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
16 * pre-determined set of performance points.
19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
28 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
36 /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
39 /* MAX_POST_DIVIDE_REF_FREQ: maximum post-divider reference frequency, in Hz */
68 * __wrpll_calc_filter_range() - determine PLL loop filter bandwidth
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| /kernel/linux/linux-6.6/drivers/clk/analogbits/ |
| D | wrpll-cln28hpc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
16 * pre-determined set of performance points.
19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
32 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
40 /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
43 /* MAX_POST_DIVIDE_REF_FREQ: maximum post-divider reference frequency, in Hz */
72 * __wrpll_calc_filter_range() - determine PLL loop filter bandwidth
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| /kernel/linux/linux-6.6/arch/powerpc/sysdev/ |
| D | fsl_lbc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright © 2007-2008 MontaVista Software, Inc.
10 * Author: Roy Zang <tie-fei.zang@freescale.com>
36 * fsl_lbc_addr - convert the base address
46 struct device_node *np = fsl_lbc_ctrl_dev->dev->of_node; in fsl_lbc_addr()
57 * fsl_lbc_find - find Localbus bank
70 if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs) in fsl_lbc_find()
71 return -ENODEV; in fsl_lbc_find()
73 lbc = fsl_lbc_ctrl_dev->regs; in fsl_lbc_find()
74 for (i = 0; i < ARRAY_SIZE(lbc->bank); i++) { in fsl_lbc_find()
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| /kernel/linux/linux-5.10/arch/powerpc/sysdev/ |
| D | fsl_lbc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright © 2007-2008 MontaVista Software, Inc.
10 * Author: Roy Zang <tie-fei.zang@freescale.com>
35 * fsl_lbc_addr - convert the base address
45 struct device_node *np = fsl_lbc_ctrl_dev->dev->of_node; in fsl_lbc_addr()
56 * fsl_lbc_find - find Localbus bank
69 if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs) in fsl_lbc_find()
70 return -ENODEV; in fsl_lbc_find()
72 lbc = fsl_lbc_ctrl_dev->regs; in fsl_lbc_find()
73 for (i = 0; i < ARRAY_SIZE(lbc->bank); i++) { in fsl_lbc_find()
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| /kernel/linux/linux-5.10/Documentation/leds/ |
| D | leds-lm3556.rst | 6 1.5 A Synchronous Boost LED Flash Driver w/ High-Side Current Source
10 - Daniel Jeong
12 Contact:Daniel Jeong(daniel.jeong-at-ti.com, gshark.jeong-at-gmail.com)
15 -----------
50 In Torch Mode, the current source(LED) is programmed via the CURRENT CONTROL
78 and 4 patterns are pre-defined in indicator_pattern array.
80 According to N-lank, Pulse time and N Period values, different pattern wiill
84 Please refer datasheet for more detail about N-Blank, Pulse time and N Period.
118 -----
121 according to include/linux/platform_data/leds-lm3556.h, set the i2c board info
|
| /kernel/linux/linux-5.10/drivers/power/supply/ |
| D | smb347-charger.c | 1 // SPDX-License-Identifier: GPL-2.0-only
23 #include <dt-bindings/power/summit,smb347-charger.h>
26 #define SMB3XX_SOFT_TEMP_COMPENSATE_DEFAULT -1
28 /* Use default factory programmed value for hard/soft temperature limit */
29 #define SMB3XX_TEMP_USE_DEFAULT -273
34 * reloaded from non-volatile registers after POR.
132 * struct smb347_charger - smb347 charger instance
144 * @pre_charge_current: current (in uA) to use in pre-charging phase
148 * pre-charge to fast charge mode
153 * current [%100 - %130] (in degree C)
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/iio/adc/ |
| D | qcom,spmi-vadc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/qcom,spmi-vadc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
15 voltage. The VADC is a 15-bit sigma-delta ADC.
17 voltage. The VADC is a 16-bit sigma-delta ADC.
22 - items:
23 - const: qcom,pms405-adc
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| /kernel/linux/linux-6.6/Documentation/leds/ |
| D | leds-lm3556.rst | 6 1.5 A Synchronous Boost LED Flash Driver w/ High-Side Current Source
10 - Daniel Jeong
12 Contact:Daniel Jeong(daniel.jeong-at-ti.com, gshark.jeong-at-gmail.com)
15 -----------
50 In Torch Mode, the current source(LED) is programmed via the CURRENT CONTROL
78 and 4 patterns are pre-defined in indicator_pattern array.
80 According to N-lank, Pulse time and N Period values, different pattern wiill
84 Please refer datasheet for more detail about N-Blank, Pulse time and N Period.
118 -----
121 according to include/linux/platform_data/leds-lm3556.h, set the i2c board info
|
| /kernel/linux/linux-6.6/drivers/power/supply/ |
| D | smb347-charger.c | 1 // SPDX-License-Identifier: GPL-2.0-only
23 #include <dt-bindings/power/summit,smb347-charger.h>
26 #define SMB3XX_SOFT_TEMP_COMPENSATE_DEFAULT -1
28 /* Use default factory programmed value for hard/soft temperature limit */
29 #define SMB3XX_TEMP_USE_DEFAULT -273
34 * reloaded from non-volatile registers after POR.
136 * struct smb347_charger - smb347 charger instance
149 * @pre_charge_current: current (in uA) to use in pre-charging phase
153 * pre-charge to fast charge mode
158 * current [%100 - %130] (in degree C)
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/iio/adc/ |
| D | qcom,spmi-vadc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/qcom,spmi-vadc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
15 voltage. The VADC is a 15-bit sigma-delta ADC.
17 voltage. The VADC is a 16-bit sigma-delta ADC.
22 - items:
23 - const: qcom,pms405-adc
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/ |
| D | intel_dp_aux_backlight.c | 34 if (!(intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)) in set_aux_backlight_enable()
37 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, in set_aux_backlight_enable()
39 drm_dbg_kms(&i915->drm, "Failed to read DPCD register 0x%x\n", in set_aux_backlight_enable()
48 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, in set_aux_backlight_enable()
50 drm_dbg_kms(&i915->drm, "Failed to %s aux backlight\n", in set_aux_backlight_enable()
61 if (drm_dp_dpcd_readb(&intel_dp->aux, in intel_dp_aux_backlight_dpcd_mode()
64 drm_dbg_kms(&i915->drm, in intel_dp_aux_backlight_dpcd_mode()
76 * on if 8-bit(MSB) or 16-bit(MSB and LSB) values are supported
86 * If we're not in DPCD control mode yet, the programmed brightness in intel_dp_aux_get_backlight()
90 return connector->panel.backlight.max; in intel_dp_aux_get_backlight()
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