| /kernel/linux/linux-5.10/Documentation/ABI/testing/ |
| D | sysfs-class-remoteproc | 4 Description: Remote processor firmware
7 remote processor.
9 To change the running firmware, ensure the remote processor is
15 Description: Remote processor state
17 Reports the state of the remote processor, which will be one of:
25 "offline" means the remote processor is powered off.
27 "suspended" means that the remote processor is suspended and
30 "running" is the normal state of an available remote processor
33 the remote processor.
35 "invalid" is returned if the remote processor is in an
[all …]
|
| /kernel/linux/linux-6.6/Documentation/ABI/testing/ |
| D | sysfs-class-remoteproc | 4 Description: Remote processor firmware
7 remote processor.
9 To change the running firmware, ensure the remote processor is
15 Description: Remote processor state
17 Reports the state of the remote processor, which will be one of:
25 "offline" means the remote processor is powered off.
27 "suspended" means that the remote processor is suspended and
30 "running" is the normal state of an available remote processor
33 the remote processor.
35 "invalid" is returned if the remote processor is in an
[all …]
|
| /kernel/linux/linux-5.10/arch/sh/ |
| D | Kconfig | 77 The SuperH is a RISC processor targeted for use in embedded systems
154 # Processor families
216 prompt "Processor sub-type selection"
219 # Processor subtypes
222 # SH-2 Processor Support
225 bool "Support SH7619 processor"
230 bool "Support J2 processor"
235 # SH-2A Processor Support
238 bool "Support SH7201 processor"
244 bool "Support SH7203 processor"
[all …]
|
| /kernel/linux/linux-6.6/arch/sh/ |
| D | Kconfig | 78 The SuperH is a RISC processor targeted for use in embedded systems
152 # Processor families
214 prompt "Processor sub-type selection"
217 # Processor subtypes
220 # SH-2 Processor Support
223 bool "Support SH7619 processor"
228 bool "Support J2 processor"
233 # SH-2A Processor Support
236 bool "Support SH7201 processor"
242 bool "Support SH7203 processor"
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/powerpc/power8/ |
| D | cache.json | 5 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
6 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another …
11 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…
12 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch…
17 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…
18 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen…
23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand …
24 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o…
35 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local …
36 …"PublicDescription": "The processor's data cache was reloaded from a location other than the local…
[all …]
|
| D | frontend.json | 89 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an…
90 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a…
95 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot…
96 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano…
101 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a di…
102 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a d…
107 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on …
108 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's memory on…
113 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 due to an…
114 …"PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 due to e…
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/powerpc/power8/ |
| D | cache.json | 5 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
6 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another …
11 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…
12 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch…
17 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…
18 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen…
23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand …
24 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o…
35 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local …
36 …"PublicDescription": "The processor's data cache was reloaded from a location other than the local…
[all …]
|
| D | frontend.json | 89 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an…
90 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a…
95 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot…
96 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano…
101 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a di…
102 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a d…
107 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on …
108 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's memory on…
113 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 due to an…
114 …"PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 due to e…
[all …]
|
| /kernel/linux/linux-5.10/drivers/eisa/ |
| D | eisa.ids | 74 AIR1001 "AIR P6NDP PCI/EISA Dual-Pentium Processor System Board"
84 ALR3000 "80486 Processor Module"
85 ALR3010 "Pentium Processor Board"
91 ALRB0A0 "Primary System Processor Board - 80486DX2/66"
92 ALRB0B0 "Secondary System Processor Board - 80486DX2/66"
245 CPQ5000 "Compaq 386/33 System Processor Board used as Secondary"
246 CPQ5251 "Compaq 5/133 System Processor Board-2MB"
247 CPQ5253 "Compaq 5/166 System Processor Board-2MB"
248 CPQ5255 "Compaq 5/133 System Processor Board-1MB"
249 CPQ525D "Compaq 5/100 System Processor Board-1MB"
[all …]
|
| /kernel/linux/linux-6.6/drivers/eisa/ |
| D | eisa.ids | 74 AIR1001 "AIR P6NDP PCI/EISA Dual-Pentium Processor System Board"
84 ALR3000 "80486 Processor Module"
85 ALR3010 "Pentium Processor Board"
91 ALRB0A0 "Primary System Processor Board - 80486DX2/66"
92 ALRB0B0 "Secondary System Processor Board - 80486DX2/66"
245 CPQ5000 "Compaq 386/33 System Processor Board used as Secondary"
246 CPQ5251 "Compaq 5/133 System Processor Board-2MB"
247 CPQ5253 "Compaq 5/166 System Processor Board-2MB"
248 CPQ5255 "Compaq 5/133 System Processor Board-1MB"
249 CPQ525D "Compaq 5/100 System Processor Board-1MB"
[all …]
|
| /kernel/linux/linux-6.6/arch/arm/mach-imx/ |
| D | Kconfig | 47 This enables support for Freescale i.MX31 processor
54 This enables support for Freescale i.MX35 processor
66 This enables support for Freescale i.MX1 processor
78 This enables support for Freescale i.MX25 processor
86 This enables support for Freescale i.MX27 processor
105 This enables support for Freescale i.MX50 processor.
112 This enables support for Freescale i.MX51 processor
120 This enables support for Freescale i.MX53 processor.
144 This enables support for Freescale i.MX6 Quad processor.
154 This enables support for Freescale i.MX6 SoloLite processor.
[all …]
|
| /kernel/linux/linux-5.10/arch/m68k/ |
| D | Kconfig.cpu | 2 comment "Processor Type"
10 the full 68000 processor instruction set.
12 of the 68000 processor family. They are mainly targeted at embedded
15 processor instruction set.
17 MC68xxx processor, select M68KCLASSIC.
19 processor, select COLDFIRE.
63 based on the 68020 processor. For the most part it is used in
73 processor, say Y. Otherwise, say N. Note that the 68020 requires a
84 processor, say Y. Otherwise, say N. Note that a MC68EC030 will not
94 or MC68040 processor, say Y. Otherwise, say N. Note that an
[all …]
|
| /kernel/linux/linux-5.10/drivers/net/phy/mscc/ |
| D | mscc_ptp.c | 23 /* Two PHYs share the same 1588 processor and it's to be entirely configured
24 * through the base PHY of this processor.
59 PROCESSOR, enumerator
77 case PROCESSOR: in vsc85xx_ts_read_csr()
117 blk == PROCESSOR; in vsc85xx_ts_write_csr()
127 case PROCESSOR: in vsc85xx_ts_write_csr()
254 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_STALL_LATENCY, in vsc85xx_ts_set_latencies()
274 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_LOCAL_LATENCY, in vsc85xx_ts_set_latencies()
277 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_ts_set_latencies()
280 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_TSP_CTRL, in vsc85xx_ts_set_latencies()
[all …]
|
| /kernel/linux/linux-6.6/drivers/net/phy/mscc/ |
| D | mscc_ptp.c | 23 /* Two PHYs share the same 1588 processor and it's to be entirely configured
24 * through the base PHY of this processor.
59 PROCESSOR, enumerator
77 case PROCESSOR: in vsc85xx_ts_read_csr()
117 blk == PROCESSOR; in vsc85xx_ts_write_csr()
127 case PROCESSOR: in vsc85xx_ts_write_csr()
254 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_STALL_LATENCY, in vsc85xx_ts_set_latencies()
274 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_LOCAL_LATENCY, in vsc85xx_ts_set_latencies()
277 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_ts_set_latencies()
280 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_TSP_CTRL, in vsc85xx_ts_set_latencies()
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/mach-imx/ |
| D | Kconfig | 59 This enables support for Freescale i.MX31 processor
66 This enables support for Freescale i.MX31 processor
78 This enables support for Freescale i.MX1 processor
90 This enables support for Freescale i.MX25 processor
98 This enables support for Freescale i.MX27 processor
117 This enables support for Freescale i.MX50 processor.
124 This enables support for Freescale i.MX51 processor
132 This enables support for Freescale i.MX53 processor.
156 This enables support for Freescale i.MX6 Quad processor.
166 This enables support for Freescale i.MX6 SoloLite processor.
[all …]
|
| /kernel/linux/linux-6.6/Documentation/powerpc/ |
| D | elf_hwcaps.rst | 80 The processor is PowerPC 601.
93 The processor is 40x or 44x family.
96 The processor has a unified L1 cache for instructions and data, as
98 Unused in the kernel since 39c8bf2b3cc1 ("powerpc: Retire e200 core (mpc555x processor)")
111 This is a 601 specific HWCAP, so if it is known that the processor
117 The processor is POWER4 or PPC970/FX/MP.
121 The processor is POWER5.
124 The processor is POWER5+.
127 The processor is Cell.
130 The processor implements the embedded category ("BookE") architecture.
[all …]
|
| /kernel/linux/linux-6.6/arch/m68k/ |
| D | Kconfig.cpu | 2 comment "Processor Type"
10 the full 68000 processor instruction set.
12 of the 68000 processor family. They are mainly targeted at embedded
15 processor instruction set.
17 MC68xxx processor, select M68KCLASSIC.
19 processor, select COLDFIRE.
63 processor, say Y. Otherwise, say N. Note that the 68020 requires a
74 processor, say Y. Otherwise, say N. Note that a MC68EC030 will not
84 or MC68040 processor, say Y. Otherwise, say N. Note that an
95 processor, say Y. Otherwise, say N.
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,smsm.txt | 4 information between the processors in a Qualcomm SoC. Each processor is
5 assigned 32 bits of state that can be modified. A processor can through a
7 certain bit owned by a certain remote processor.
19 signaling the N:th remote processor
27 Definition: identifier of the local processor in the list of hosts, or
29 matrix representing the local processor
43 Each processor's state bits are described by a subnode of the smsm device node.
45 processor's state bits or the local processors bits. The node names are not
63 to belong to a remote processor
73 Definition: one entry specifying remote IRQ used by the remote processor
[all …]
|
| /kernel/linux/linux-5.10/Documentation/admin-guide/pm/ |
| D | intel_idle.rst | 20 a particular processor model in it depends on whether or not it recognizes that
21 processor model and may also depend on information coming from the platform
26 ``intel_idle`` uses the ``MWAIT`` instruction to inform the processor that the
28 processor's functional blocks into low-power states. That instruction takes two
30 first of which, referred to as a *hint*, can be used by the processor to
47 Each ``MWAIT`` hint value is interpreted by the processor as a license to
48 reconfigure itself in a certain way in order to save energy. The processor
52 processor) corresponding to them depends on the processor model and it may also
58 for different processor models included in the driver itself and the ACPI tables
59 of the system. The former are always used if the processor model at hand is
[all …]
|
| /kernel/linux/linux-6.6/Documentation/admin-guide/pm/ |
| D | intel_idle.rst | 20 a particular processor model in it depends on whether or not it recognizes that
21 processor model and may also depend on information coming from the platform
26 ``intel_idle`` uses the ``MWAIT`` instruction to inform the processor that the
28 processor's functional blocks into low-power states. That instruction takes two
30 first of which, referred to as a *hint*, can be used by the processor to
47 Each ``MWAIT`` hint value is interpreted by the processor as a license to
48 reconfigure itself in a certain way in order to save energy. The processor
52 processor) corresponding to them depends on the processor model and it may also
59 for different processor models included in the driver itself and the ACPI tables
60 of the system. The former are always used if the processor model at hand is
[all …]
|
| /kernel/linux/linux-6.6/drivers/remoteproc/ |
| D | Kconfig | 5 bool "Support for Remote Processor subsystem"
33 processor framework.
44 processor framework.
62 Say y here to support Mediatek's System Companion Processor (SCP) via
63 the remote processor framework.
75 and DSP on OMAP4) via the remote processor framework.
102 Say y here to support Wakeup M3 remote processor on TI AM33xx
116 remote processor framework.
136 via the remote processor framework.
142 tristate "Amlogic Meson6/8/8b/8m2 AO ARC remote processor support"
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/ivybridge/ |
| D | uncore.json | 7 "BriefDescription": "A snoop misses in some processor core.",
8 "PublicDescription": "A snoop misses in some processor core.",
19 "BriefDescription": "A snoop invalidates a non-modified line in some processor core.",
20 "PublicDescription": "A snoop invalidates a non-modified line in some processor core.",
31 "BriefDescription": "A snoop hits a non-modified line in some processor core.",
32 "PublicDescription": "A snoop hits a non-modified line in some processor core.",
43 "BriefDescription": "A snoop hits a modified line in some processor core.",
44 "PublicDescription": "A snoop hits a modified line in some processor core.",
55 "BriefDescription": "A snoop invalidates a modified line in some processor core.",
56 "PublicDescription": "A snoop invalidates a modified line in some processor core.",
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/sandybridge/ |
| D | uncore.json | 7 "BriefDescription": "A snoop misses in some processor core.",
8 "PublicDescription": "A snoop misses in some processor core.",
19 "BriefDescription": "A snoop invalidates a non-modified line in some processor core.",
20 "PublicDescription": "A snoop invalidates a non-modified line in some processor core.",
31 "BriefDescription": "A snoop hits a non-modified line in some processor core.",
32 "PublicDescription": "A snoop hits a non-modified line in some processor core.",
43 "BriefDescription": "A snoop hits a modified line in some processor core.",
44 "PublicDescription": "A snoop hits a modified line in some processor core.",
55 "BriefDescription": "A snoop invalidates a modified line in some processor core.",
56 "PublicDescription": "A snoop invalidates a modified line in some processor core.",
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/ |
| D | fsl,mu-msi.yaml | 16 for one processor (A side) to signal the other processor (B side) using
23 registers (Processor A-side, Processor B-side).
45 - const: processor-a-side
46 - const: processor-b-side
62 - const: processor-a-side
63 - const: processor-b-side
94 reg-names = "processor-a-side", "processor-b-side";
98 power-domain-names = "processor-a-side", "processor-b-side";
|
| /kernel/linux/linux-5.10/arch/mips/include/asm/ |
| D | war.h | 17 * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
19 * "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
24 * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
29 * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
43 * "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
44 * "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
56 * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
60 * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
62 * "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
64 * "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
[all …]
|