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/kernel/linux/linux-6.6/drivers/clocksource/
Dsamsung_pwm_timer.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * samsung - Common hr-timer support (s3c and s5p)
29 #define REG_TCFG0 0x00
30 #define REG_TCFG1 0x04
31 #define REG_TCON 0x08
32 #define REG_TINT_CSTAT 0x44
34 #define REG_TCNTB(chan) (0x0c + 12 * (chan))
35 #define REG_TCMPB(chan) (0x10 + 12 * (chan))
37 #define TCFG0_PRESCALER_MASK 0xff
41 #define TCFG1_MUX_MASK 0xf
[all …]
/kernel/linux/linux-5.10/drivers/pwm/
Dcore.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 2011-2012 Avionic Design GmbH
11 #include <linux/pwm.h>
12 #include <linux/radix-tree.h>
21 #include <dt-bindings/pwm/pwm.h>
24 #include <trace/events/pwm.h>
35 static struct pwm_device *pwm_to_device(unsigned int pwm) in pwm_to_device() argument
37 return radix_tree_lookup(&pwm_tree, pwm); in pwm_to_device()
40 static int alloc_pwms(int pwm, unsigned int count) in alloc_pwms() argument
42 unsigned int from = 0; in alloc_pwms()
[all …]
Dpwm-renesas-tpu.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Mobile TPU PWM driver
18 #include <linux/pwm.h>
24 #define TPU_TSTR 0x00 /* Timer start register (shared) */
26 #define TPU_TCRn 0x00 /* Timer control register */
27 #define TPU_TCR_CCLR_NONE (0 << 5)
32 #define TPU_TCR_CKEG_RISING (0 << 3)
35 #define TPU_TMDRn 0x04 /* Timer mode register */
39 #define TPU_TMDR_MD_NORMAL (0 << 0)
40 #define TPU_TMDR_MD_PWM (2 << 0)
[all …]
Dpwm-berlin.c2 * Marvell Berlin PWM driver
6 * Author: Antoine Tenart <antoine.tenart@free-electrons.com>
18 #include <linux/pwm.h>
21 #define BERLIN_PWM_EN 0x0
22 #define BERLIN_PWM_ENABLE BIT(0)
23 #define BERLIN_PWM_CONTROL 0x4
29 * bits. So, the max TCNT that actually works for a modulus of 4 is 0x3fff;
30 * for 8, 0x1fff; and so on. This means that those moduli are entirely
35 #define BERLIN_PWM_PRESCALE_4096 0x7
37 #define BERLIN_PWM_DUTY 0x8
[all …]
Dpwm-pxa.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/pwm/pwm-pxa.c
5 * simple driver for PWM (Pulse Width Modulator) controller
7 * 2008-02-13 initial version
18 #include <linux/pwm.h>
23 #define HAS_SECONDARY_PWM 0x10
26 /* PWM has_secondary_pwm? */
27 { "pxa25x-pwm", 0 },
28 { "pxa27x-pwm", HAS_SECONDARY_PWM },
29 { "pxa168-pwm", 0 },
[all …]
Dpwm-twl.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/pwm.h>
22 #define TWL_PWM_MAX 0x7f
25 #define TWL4030_GPBR1_REG 0x0c
26 #define TWL4030_PMBR1_REG 0x0d
29 #define TWL4030_PWMXCLK_ENABLE (1 << 0)
32 #define TWL4030_PWM_TOGGLE(pwm, x) ((x) << (pwm)) argument
35 #define TWL4030_GPIO6_PWM0_MUTE_MASK (0x03 << 2)
36 #define TWL4030_GPIO6_PWM0_MUTE_PWM0 (0x01 << 2)
37 #define TWL4030_GPIO7_VIBRASYNC_PWM1_MASK (0x03 << 4)
[all …]
Dpwm-sun4i.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
8 * - When outputing the source clock directly, the PWM logic will be bypassed
22 #include <linux/pwm.h>
28 #define PWM_CTRL_REG 0x0
30 #define PWM_CH_PRD_BASE 0x4
31 #define PWM_CH_PRD_OFFSET 0x4
35 #define PWM_PRESCAL_MASK GENMASK(3, 0)
36 #define PWM_PRESCAL_OFF 0
48 #define PWM_PRD(prd) (((prd) - 1) << 16)
[all …]
Dsysfs.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * A simple sysfs interface for the generic PWM framework
15 #include <linux/pwm.h>
19 struct pwm_device *pwm; member
33 return export->pwm; in child_to_pwm_device()
40 const struct pwm_device *pwm = child_to_pwm_device(child); in period_show() local
43 pwm_get_state(pwm, &state); in period_show()
53 struct pwm_device *pwm = export->pwm; in period_store() local
58 ret = kstrtou64(buf, 0, &val); in period_store()
62 mutex_lock(&export->lock); in period_store()
[all …]
Dpwm-stmpe.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/pwm.h>
18 #define STMPE24XX_PWMCS 0x30
19 #define PWMCS_EN_PWM0 BIT(0)
22 #define STMPE24XX_PWMIC0 0x38
23 #define STMPE24XX_PWMIC1 0x39
24 #define STMPE24XX_PWMIC2 0x3a
39 static int stmpe_24xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) in stmpe_24xx_pwm_enable() argument
45 ret = stmpe_reg_read(stmpe_pwm->stmpe, STMPE24XX_PWMCS); in stmpe_24xx_pwm_enable()
46 if (ret < 0) { in stmpe_24xx_pwm_enable()
[all …]
Dpwm-tegra.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/pwm/pwm-tegra.c
5 * Tegra pulse-width-modulation controller driver
7 * Copyright (c) 2010-2020, NVIDIA Corporation.
8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
11 * 1. 13-bit: Frequency division (SCALE)
12 * 2. 8-bit : Pulse division (DUTY)
13 * 3. 1-bit : Enable bit
15 * The PWM clock frequency is divided by 256 before subdividing it based
17 * frequency for PWM output. The maximum output frequency that can be
[all …]
/kernel/linux/linux-5.10/drivers/clocksource/
Dsamsung_pwm_timer.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * samsung - Common hr-timer support (s3c and s5p)
30 #define REG_TCFG0 0x00
31 #define REG_TCFG1 0x04
32 #define REG_TCON 0x08
33 #define REG_TINT_CSTAT 0x44
35 #define REG_TCNTB(chan) (0x0c + 12 * (chan))
36 #define REG_TCMPB(chan) (0x10 + 12 * (chan))
38 #define TCFG0_PRESCALER_MASK 0xff
42 #define TCFG1_MUX_MASK 0xf
[all …]
/kernel/linux/linux-6.6/drivers/pwm/
Dcore.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 2011-2012 Avionic Design GmbH
12 #include <linux/pwm.h>
21 #include <dt-bindings/pwm/pwm.h>
24 #include <trace/events/pwm.h>
42 start = bitmap_find_next_zero_area(allocated_pwms, MAX_PWMS, 0, in alloc_pwms()
43 count, 0); in alloc_pwms()
46 return -ENOSPC; in alloc_pwms()
56 bitmap_clear(allocated_pwms, chip->base, chip->npwm); in free_pwms()
58 kfree(chip->pwms); in free_pwms()
[all …]
Dpwm-twl.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/pwm.h>
22 #define TWL_PWM_MAX 0x7f
25 #define TWL4030_GPBR1_REG 0x0c
26 #define TWL4030_PMBR1_REG 0x0d
29 #define TWL4030_PWMXCLK_ENABLE (1 << 0)
32 #define TWL4030_PWM_TOGGLE(pwm, x) ((x) << (pwm)) argument
35 #define TWL4030_GPIO6_PWM0_MUTE_MASK (0x03 << 2)
36 #define TWL4030_GPIO6_PWM0_MUTE_PWM0 (0x01 << 2)
37 #define TWL4030_GPIO7_VIBRASYNC_PWM1_MASK (0x03 << 4)
[all …]
Dsysfs.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * A simple sysfs interface for the generic PWM framework
15 #include <linux/pwm.h>
19 struct pwm_device *pwm; member
33 return export->pwm; in child_to_pwm_device()
40 const struct pwm_device *pwm = child_to_pwm_device(child); in period_show() local
43 pwm_get_state(pwm, &state); in period_show()
53 struct pwm_device *pwm = export->pwm; in period_store() local
58 ret = kstrtou64(buf, 0, &val); in period_store()
62 mutex_lock(&export->lock); in period_store()
[all …]
Dpwm-vt8500.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/pwm/pwm-vt8500.c
16 #include <linux/pwm.h>
28 #define REG_CTRL(pwm) (((pwm) << 4) + 0x00) argument
29 #define REG_SCALAR(pwm) (((pwm) << 4) + 0x04) argument
30 #define REG_PERIOD(pwm) (((pwm) << 4) + 0x08) argument
31 #define REG_DUTY(pwm) (((pwm) << 4) + 0x0C) argument
32 #define REG_STATUS 0x40
34 #define CTRL_ENABLE BIT(0)
41 #define STATUS_CTRL_UPDATE BIT(0)
[all …]
Dpwm-twl-led.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * This driver is a complete rewrite of the former pwm-twl6030.c authorded by:
15 * - The twl6030 hardware only supports two period lengths (128 clock ticks and
17 * - The hardware doesn't support ON = 0, so the active part of a period doesn't
19 * - The hardware could support inverted polarity (with a similar limitation as
21 * - The hardware emits a constant low output when disabled.
22 * - A request for .duty_cycle = 0 results in an output wave with one active
24 * - The driver only implements setting the relative duty cycle.
25 * - The driver doesn't implement .get_state().
31 #include <linux/pwm.h>
[all …]
Dpwm-stmpe.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/pwm.h>
18 #define STMPE24XX_PWMCS 0x30
19 #define PWMCS_EN_PWM0 BIT(0)
22 #define STMPE24XX_PWMIC0 0x38
23 #define STMPE24XX_PWMIC1 0x39
24 #define STMPE24XX_PWMIC2 0x3a
39 static int stmpe_24xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) in stmpe_24xx_pwm_enable() argument
45 ret = stmpe_reg_read(stmpe_pwm->stmpe, STMPE24XX_PWMCS); in stmpe_24xx_pwm_enable()
46 if (ret < 0) { in stmpe_24xx_pwm_enable()
[all …]
/kernel/linux/linux-6.6/include/linux/
Dpwm.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 * enum pwm_polarity - polarity of a PWM signal
13 * @PWM_POLARITY_NORMAL: a high signal for the duration of the duty-
16 * @PWM_POLARITY_INVERSED: a low signal for the duration of the duty-
26 * struct pwm_args - board-dependent PWM arguments
30 * This structure describes board-dependent arguments attached to a PWM
31 * device. These arguments are usually retrieved from the PWM lookup table or
34 * Do not confuse this with the PWM state: PWM arguments represent the initial
35 * configuration that users want to use on this PWM device rather than the
36 * current PWM hardware state.
[all …]
/kernel/linux/linux-5.10/include/linux/
Dpwm.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 * enum pwm_polarity - polarity of a PWM signal
16 * @PWM_POLARITY_NORMAL: a high signal for the duration of the duty-
19 * @PWM_POLARITY_INVERSED: a low signal for the duration of the duty-
29 * struct pwm_args - board-dependent PWM arguments
33 * This structure describes board-dependent arguments attached to a PWM
34 * device. These arguments are usually retrieved from the PWM lookup table or
37 * Do not confuse this with the PWM state: PWM arguments represent the initial
38 * configuration that users want to use on this PWM device rather than the
39 * current PWM hardware state.
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pwm/
Dpwm-samsung.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/pwm-samsung.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC PWM timers
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 Samsung SoCs contain PWM timer blocks which can be used for system clock source
15 and clock event timers, as well as to drive SoC outputs with PWM signal. Each
16 PWM timer block provides 5 PWM channels (not all of them can drive physical
[all …]
Drenesas,pwm-rcar.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/renesas,pwm-rcar.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car PWM Timer Controller
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,pwm-r8a7742 # RZ/G1H
17 - renesas,pwm-r8a7743 # RZ/G1M
18 - renesas,pwm-r8a7744 # RZ/G1N
[all …]
Dpwm.txt1 Specifying PWM information for devices
4 1) PWM user nodes
5 -----------------
7 PWM users should specify a list of PWM devices that they want to use
8 with a property containing a 'pwm-list':
10 pwm-list ::= <single-pwm> [pwm-list]
11 single-pwm ::= <pwm-phandle> <pwm-specifier>
12 pwm-phandle : phandle to PWM controller node
13 pwm-specifier : array of #pwm-cells specifying the given PWM
16 PWM properties should be named "pwms". The exact meaning of each pwms
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pwm/
Dpwm-samsung.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/pwm-samsung.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC PWM timers
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 Samsung SoCs contain PWM timer blocks which can be used for system clock source
15 and clock event timers, as well as to drive SoC outputs with PWM signal. Each
16 PWM timer block provides 5 PWM channels (not all of them can drive physical
[all …]
Dpwm.txt1 Specifying PWM information for devices
4 1) PWM user nodes
5 -----------------
7 PWM users should specify a list of PWM devices that they want to use
8 with a property containing a 'pwm-list':
10 pwm-list ::= <single-pwm> [pwm-list]
11 single-pwm ::= <pwm-phandle> <pwm-specifier>
12 pwm-phandle : phandle to PWM controller node
13 pwm-specifier : array of #pwm-cells specifying the given PWM
16 PWM properties should be named "pwms". The exact meaning of each pwms
[all …]
Drenesas,pwm-rcar.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/renesas,pwm-rcar.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car PWM Timer Controller
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,pwm-r8a7742 # RZ/G1H
17 - renesas,pwm-r8a7743 # RZ/G1M
18 - renesas,pwm-r8a7744 # RZ/G1N
[all …]

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