Searched +full:px30 +full:- +full:dsi +full:- +full:dphy (Results 1 – 12 of 12) sorted by relevance
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | rockchip,px30-dsi-dphy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Rockchip MIPI DPHY with additional LVDS/TTL modes 10 - Heiko Stuebner <heiko@sntech.de> 13 "#phy-cells": 18 - rockchip,px30-dsi-dphy 19 - rockchip,rk3128-dsi-dphy 20 - rockchip,rk3368-dsi-dphy [all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | rockchip,px30-dsi-dphy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Rockchip MIPI DPHY with additional LVDS/TTL modes 10 - Heiko Stuebner <heiko@sntech.de> 13 "#phy-cells": 18 - rockchip,px30-dsi-dphy 19 - rockchip,rk3128-dsi-dphy 20 - rockchip,rk3368-dsi-dphy [all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/rockchip/ |
| D | rockchip-lvds.txt | 5 - compatible: matching the soc type, one of 6 - "rockchip,rk3288-lvds"; 7 - "rockchip,px30-lvds"; 9 - reg: physical base address of the controller and length 11 - clocks: must include clock specifiers corresponding to entries in the 12 clock-names property. 13 - clock-names: must contain "pclk_lvds" 15 - avdd1v0-supply: regulator phandle for 1.0V analog power 16 - avdd1v8-supply: regulator phandle for 1.8V analog power 17 - avdd3v3-supply: regulator phandle for 3.3V analog power [all …]
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| D | dw_mipi_dsi_rockchip.txt | 1 Rockchip specific extensions to the Synopsys Designware MIPI DSI 5 - #address-cells: Should be <1>. 6 - #size-cells: Should be <0>. 7 - compatible: one of 8 "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi" 9 "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi" 10 "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi" 11 - reg: Represent the physical address range of the controller. 12 - interrupts: Represent the controller's interrupt to the CPU(s). 13 - clocks, clock-names: Phandles to the controller's pll reference [all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/rockchip/ |
| D | rockchip,dw-mipi-dsi.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Rockchip specific extensions to the Synopsys Designware MIPI DSI 10 - Sandy Huang <hjc@rock-chips.com> 11 - Heiko Stuebner <heiko@sntech.de> 16 - enum: 17 - rockchip,px30-mipi-dsi 18 - rockchip,rk3288-mipi-dsi [all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/rockchip/ |
| D | px30.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/clock/px30-cru.h> 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/interrupt-controller/irq.h> 10 #include <dt-bindings/pinctrl/rockchip.h> 11 #include <dt-bindings/power/px30-power.h> 12 #include <dt-bindings/soc/rockchip,boot-mode.h> 13 #include <dt-bindings/thermal/thermal.h> 16 compatible = "rockchip,px30"; [all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/rockchip/ |
| D | dw-mipi-dsi-rockchip.c | 1 // SPDX-License-Identifier: GPL-2.0+ 5 * Chris Zhong <zyw@rock-chips.com> 6 * Nickey Yang <nickey.yang@rock-chips.com> 41 #define N_LANES(n) ((((n) - 1) & 0x3) << 0) 93 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f) 96 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f) 97 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf) 264 /* dual-channel */ 268 /* optional external dphy */ 275 struct phy *dphy; member [all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/rockchip/ |
| D | dw-mipi-dsi-rockchip.c | 1 // SPDX-License-Identifier: GPL-2.0+ 5 * Chris Zhong <zyw@rock-chips.com> 6 * Nickey Yang <nickey.yang@rock-chips.com> 40 #define N_LANES(n) ((((n) - 1) & 0x3) << 0) 92 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f) 95 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f) 96 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf) 230 /* dual-channel */ 234 /* optional external dphy */ 255 /* The table is based on 27MHz DPHY pll reference clock. */ [all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/rockchip/ |
| D | px30.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/clock/px30-cru.h> 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/interrupt-controller/irq.h> 10 #include <dt-bindings/pinctrl/rockchip.h> 11 #include <dt-bindings/power/px30-power.h> 12 #include <dt-bindings/soc/rockchip,boot-mode.h> 13 #include <dt-bindings/thermal/thermal.h> 16 compatible = "rockchip,px30"; [all …]
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| /kernel/linux/linux-6.6/drivers/phy/rockchip/ |
| D | phy-rockchip-inno-dsidphy.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Author: Wyon Bi <bivvy.bi@rock-chips.com> 12 #include <linux/clk-provider.h> 24 #include <linux/phy/phy-mipi-dphy.h> 290 orig = readl(inno->phy_base + reg); in phy_update_bits() 293 writel(tmp, inno->phy_base + reg); in phy_update_bits() 299 unsigned long prate = clk_get_rate(inno->ref_clk); in inno_dsidphy_pll_calc_rate() 310 * PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2 in inno_dsidphy_pll_calc_rate() 343 delta = abs(fout - tmp); in inno_dsidphy_pll_calc_rate() 358 inno->pll.prediv = best_prediv; in inno_dsidphy_pll_calc_rate() [all …]
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| /kernel/linux/linux-5.10/drivers/phy/rockchip/ |
| D | phy-rockchip-inno-dsidphy.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Author: Wyon Bi <bivvy.bi@rock-chips.com> 11 #include <linux/clk-provider.h> 19 #include <linux/phy/phy-mipi-dphy.h> 213 orig = readl(inno->phy_base + reg); in phy_update_bits() 216 writel(tmp, inno->phy_base + reg); in phy_update_bits() 222 unsigned long prate = clk_get_rate(inno->ref_clk); in inno_dsidphy_pll_calc_rate() 233 * PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2 in inno_dsidphy_pll_calc_rate() 266 delta = abs(fout - tmp); in inno_dsidphy_pll_calc_rate() 281 inno->pll.prediv = best_prediv; in inno_dsidphy_pll_calc_rate() [all …]
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| /kernel/linux/patches/linux-5.10/yangfan_patch/ |
| D | drivers.patch | 1 diff --git a/drivers/Makefile b/drivers/Makefile 3 --- a/drivers/Makefile 5 @@ -6,6 +6,8 @@ 6 # Rewritten to use lists instead of if-statements. 11 obj-y += irqchip/ 12 obj-y += bus/ 14 diff --git a/drivers/block/nbd.c b/drivers/block/nbd.c 16 --- a/drivers/block/nbd.c 18 @@ -2398,12 +2398,6 @@ static int nbd_genl_status(struct sk_buff *skb, struct genl_info *info) 22 - if (!dev_list) { [all …]
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